Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-03-23
2002-12-31
Mills, Gregory (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000
Reexamination Certificate
active
06500765
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a field effect transistor (FET). More particularly, the present invention relates to a method for manufacturing a FET with a dual-spacer structure.
2. Description of Related Art
When the integration of the device is increased, the energy consumption of the NMOS becomes a main problem in producing and designing integrated circuit by using NMOS as a basic element. Therefore, the COMS with a low-energy-consumption advantage is used to replace NMOS and to be a main element in manufacturing the devices.
However, because different type dopants with different diffusion rate, such as the diffusion rate of the P-type dopants is faster than that of the N-type dopants, the dopant diffusion in each source/drain region is uneven at the annual step in the formation of the source/drain region in the coexist P-type FET and N-type FET. Since the dopant diffusion of each source/drain region result is unequal, the short channel effect happens in the P-type FET when the source/drain region in N-type FET is not yet formed.
In order to improve the unequal diffusion rate mentioned above, different types of dopants with different dosage are used in the implantation process to adjust the diffusion rate of different types of dopants. Nevertheless, it is difficult to accurately control this diffusion-rate adjustment so that the shape of the source/drain region cannot be well controlled.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a field effect transistor with a dual-spacer structure. A substrate having a first device region and a second device region is provided. The first device region comprises a first gate formed over the substrate and the second device region comprises a second gate formed over the substrate. A first dielectric layer is formed over the substrate. A second dielectric layer is formed on the first dielectric layer. A portion of the second dielectric layer is removed to expose a portion of the first dielectric layer in the second device region. A portion of the remaining second dielectric layer is removed to form a first spacer on the second dielectric layer on the sidewall of the first gate. A portion of the first dielectric layer is removed to form a second spacer on the sidewall of the second gate. The first spacer and the remaining second dielectric layer between the first spacer and the first gate together form a third spacer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4775642 (1988-10-01), Chang et al.
patent: 5162884 (1992-11-01), Liou et al.
patent: 5212542 (1993-05-01), Okumura
patent: 5672531 (1997-09-01), Gardner et al.
patent: 5866460 (1999-02-01), Akram et al.
Cheng Alan
Kao Chia-Hung
Chen Kin-Chan
J.C. Patents
Mills Gregory
United Microelectronics Corp.
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