Method for manufacturing DRAM having a redundancy circuit region

Details Method for manufacturing DRAM having a redundancy circuit region Method for manufacturing DRAM having a redundancy circuit region

1998-04-20

2000-08-08

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to nonconductive state

438601, 438239, 257529, 257296, H01L 2182

Patent

active

061001171

ABSTRACT:
A method for manufacturing DRAM having a redundancy circuit region. The method utilizes a laser beam permeable layer such as a silicon nitride layer to serve as a stop layer in the etching step of the passivation oxide layer. The method removes the conductive layer, serving as the upper electrode of the capacitor, in the redundancy circuit region II. The fuse of the redundancy circuit region II can thereby be easily blown by the laser beam.

REFERENCES:
patent: 5303199 (1994-04-01), Ishihara et al.
patent: 5821160 (1998-10-01), Rodriguez et al.
patent: 5891762 (1999-04-01), Sakai et al.
patent: 5914524 (1999-06-01), Komenaka
patent: 5955380 (1999-09-01), Lee
patent: 5972756 (1999-10-01), Kono et al.

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