Method for manufacturing dielectric layer

Details Method for manufacturing dielectric layer Method for manufacturing dielectric layer

1999-09-11

2000-12-12

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438619, 438624, 438638, 438687, H01L 214763

Patent

active

061598453

ABSTRACT:
A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

REFERENCES:
patent: 5641712 (1997-06-01), Grivna
patent: 5837618 (1998-11-01), Avanzino
patent: 5872064 (1999-02-01), Huff
patent: 5949143 (1999-09-01), Bang

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