Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-05-01
2002-12-03
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000, C438S720000, C438S722000, C438S723000, C438S724000, C438S725000
Reexamination Certificate
active
06489246
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to charge-coupled image sensors and, more particularly, to a method for manufacturing such charge-coupled devices.
BACKGROUND OF THE INVENTION
Solid state charge coupled image sensing devices (CCDs) are generally classified into two types: interline transfer type or frame transfer type. The CCD array is typically composed of an array of closely spaced gates composed of polycrystalline silicon (polysilicon). Polysilicon has been a preferred material due to the ease with which a reliable thin insulating layer may be produced for insulating the separate gates from one another. In operation of frame transfer type imagers, incident light must pass through the gate electrodes and be absorbed by the underlying silicon. Thus, it is desired that these gates be transparent to a broad spectrum of wavelengths of light, and in particular to be transparent to shorter wavelengths, for example, shorter than 450 nm wavelength. Polysilicon gates are not suitable for efficient transmission of light in this wavelength range. Hence, devices utilizing more transparent conducting materials, typically composed of conducting oxide materials such as indium-tin-oxide (ITO), have been proposed. As used herein, the term ITO is to be understood to include other conducting oxide materials of other compositions as well.
U.S. Pat. No. 5,891,752 by Losee discloses a method for constructing a CCD image sensor with all ITO gates. In that device, however, the ITO gates are subjected to chemical mechanical polishing (CMP) to achieve the required electrical isolation between adjacent gates. This CMP process is inherently no-uniform over widely spaced regions and, hence, devices so produced have some variation in ITO thickness from one area of the device to another. Due to the relatively high index of refraction of the ITO material, this thickness variation results in variation in the relative amount of light which reaches the silicon substrate, and therefore, produces a spatial variation in the relative sensitivity of the device. For improved optical response, it is desirable to employ relatively thin ITO for the gates, for example, using thicknesses less than 100 nm. With decreasing ITO gate thickness, the variation in thickness caused by the CMP process causes stronger variation in the relative sensitivity of the device.
Another concern with the polished structure, particularly when thin ITO gates are desired, is due to fixed electrostatic charges which inevitably occur in overlying insulating layers of the device. Such fixed charge will cause small potential variations, usually as regions of increased electrostatic potential, immediately below the insulating gap between the CCD electrodes.
Although the presently known and utilized image sensors are satisfactory, they include the above-described drawbacks. Therefore, a need exists for uniform gate thickness in frame transfer CCD images sensors with all gates composed of ITO. A need also exists for reducing the effect of fixed charges which may be present in overlaying insulating layers. Such fixed charges can result in undesirable potential wells or barriers in the underlying silicon substrate, which, in turn, can lead to charge transfer inefficiency.
The present invention includes an image sensor for overcoming these shortcomings.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides a method of manufacturing an image sensor, the method comprising the steps providing a substrate having a gate insulating layer abutting a portion of the substrate; depositing a silicon layer on the gate insulating layer; creating a plurality of openings in the deposited silicon layer for forming a plurality of etched deposited silicon; growing an oxide on first surfaces of the etched deposited silicon which first surfaces initially form a boundary for the openings; coating photoresist in the plurality of openings between the first surfaces of the oxidized silicon; and exposing the photoresist for removing the photoresist which overlies the silicon and retains a portion of the photoresist in the openings and on the first surface of the oxidized silicon.
The above and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
REFERENCES:
patent: 4604519 (1986-08-01), Zollman et al.
patent: 4613402 (1986-09-01), Losee et al.
patent: 5240873 (1993-08-01), Shinji
patent: 5654202 (1997-08-01), Daly et al.
patent: 5891752 (1999-04-01), Losee
Knappenberger Eric J.
Losee David L.
Summa Joseph R.
Eastman Kodak Company
Tran Binh X.
Utech Benjamin L.
Watkins Peyton C.
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