Method for manufacturing capacitor structure of dynamic memory c

Details Method for manufacturing capacitor structure of dynamic memory c Method for manufacturing capacitor structure of dynamic memory c

1997-06-03

2000-02-15

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438253, 438254, 438255, 438397, 438398, H01L 218242

Patent

active

060252472

ABSTRACT:
A method is disclosed to manufacture a capacitor structure having a high capacitance and a flat topography on a semiconductor device. The method includes steps of: (a) forming a first insulating layer over a substrate having a transistor structure; (b) forming a first and a second contact holes on the first insulating layer; (c) forming a first conducting layer over the first insulating layer; (d) forming a bit line structure above the first contact hole; (e) forming an etching stop layer and a second insulating layer over the substrate, and removing a portion of the etching stop layer and the second insulating layer for forming a capacitor area wherein the second contact plug is exposed; (f) forming a second conducting layer over the substrate, and forming a sacrificial layer in the capacitor area for covering a portion of the second conducting layer; (g) forming the capacitor structure in the capacitor area.

REFERENCES:
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5488011 (1996-01-01), Figura et al.
patent: 5668038 (1997-09-01), Huang et al.
patent: 5789289 (1998-08-01), Jeng
patent: 5904521 (1999-05-01), Jeng et al.

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