Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-26
2003-01-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000
Reexamination Certificate
active
06503823
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and, more particularly, to a method for manufacturing integrated capacitive elements.
BACKGROUND OF THE INVENTION
Capacitive elements are passive components commonly used in integrated electronic circuits. A known technique for integrating metal plate capacitors on a semiconductor substrate includes the formation, after an oxide layer has been formed on the semiconductor substrate, of a metallization layer over the oxide layer. The metallization layer is patterned to provide the lower plates of the capacitive elements and any interconnection pads.
A thin lower dielectric layer is then deposited over the entire exposed surface and is intended to provide the dielectric layer separating the plates of the capacitive elements. The portions of the lower dielectric layer which overlie the metallization pads are removed by a photolithographic process. This later allows the interconnection of pads to the next metallization layer.
An upper dielectric layer is then deposited over the entire wafer surface. Subsequently, openings are formed through this dielectric layer aligned with the metallization pads and the lower dielectric layer overlying the lower plates. The upper dielectric layer has to be etchable in a completely selective manner relative to the lower dielectric layer. If the upper dielectric layer were not etchable relative to the lower dielectric layer, the lower dielectric layer might be destroyed or damaged during the formation of the contact openings, thereby compromising the operability of the capacitive elements.
The manufacturing of the capacitive elements is completed by the deposition and subsequent photolithographic definition of the next metallization level. The last-mentioned step defines the upper plates of the capacitive elements and the interconnection to the lower metallization level through the openings.
Although in many ways advantageous, the above manufacturing method includes depositing an oxide layer which is used to provide the dielectric layer between the plates of the capacitive elements. The oxide layer must have adequate characteristics to ensure functional capacitors. Consequently, the oxide layer must be suitably provided and formed in standard manufacturing schemes.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a method for manufacturing capacitive elements, in particular, high-capacitance capacitors having structural and functional features that are integratable to processes for manufacturing semiconductor-integrated electronic devices. This is done without modifying the various steps of the manufacturing processes, thereby overcoming the drawbacks of prior art processes for manufacturing capacitive elements.
Embodiments of the invention produce the aforementioned integrated capacitive elements by the very steps of a conventional process for forming interconnections in integrated circuits, in particular, a process known as “dual damascene”. More particularly, the method of this invention provides two layers of an insulating material distinguishable from each other during the removing and etching steps carried out within the multi-level interconnection scheme.
The invention specifically relates to a method for manufacturing capacitive elements on a semiconductor substrate, preferably comprising forming a first dielectric layer over the semiconductor substrate; depositing a first metallization layer on the first dielectric layer; defining the first metallization layer to provide lower plates of capacitive elements and interconnection pads in the first dielectric layer; and forming a second dielectric layer over the first dielectric layer.
The invention particularly, but not exclusively, relates to a method for manufacturing capacitive elements of high capacitance which are interposed between successive metallization levels within a multi-level connection structure, implementing in particular, the “dual damascene” interconnection scheme, and the description which follows will make reference to such a field of application for simplicity of illustration.
REFERENCES:
patent: 5219787 (1993-06-01), Carey et al.
patent: 5741721 (1998-04-01), Stevens
patent: 6242299 (2001-06-01), Hickert
patent: 0 771 022 (1997-05-01), None
patent: 0 771 022 (1997-05-01), None
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Berry Renee R
Jorgenson Lisa K.
Nelms David
STMicroelectronics S.r.l.
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