Method for manufacturing buried-channel PMOS

Details Method for manufacturing buried-channel PMOS Method for manufacturing buried-channel PMOS

1998-02-17

2000-04-18

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

438217, 438282, 438289, H01L 2122

Patent

active

060514825

ABSTRACT:
A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the method has a higher current drivability and a higher anti-punchthrough resistance.

REFERENCES:
patent: 4912065 (1990-03-01), Mizuno et al.
patent: 4927777 (1990-05-01), Hsu et al.
patent: 5266510 (1993-11-01), Lee
patent: 5401994 (1995-03-01), Adan
patent: 5476800 (1995-12-01), Burton et al.
patent: 5489543 (1996-02-01), Hong
patent: 5538913 (1996-07-01), Hong
patent: 5597752 (1997-01-01), Niwa
patent: 5625217 (1997-04-01), Chau et al.
patent: 5668021 (1997-09-01), Subramanian et al.
patent: 5681771 (1997-10-01), Hwang
patent: 5710055 (1998-01-01), Kizilyalli
patent: 5796145 (1998-08-01), Sato
patent: 5866460 (1999-02-01), Akram et al.
Felch et al, "Formation of Deep Sub-Micron Buried Channel pMOSFETs with Plasma Doping," IEEE, pp. 753-756, Oct. 1997.

Affiliated with

Also associated with

Rating

Method for manufacturing buried-channel PMOS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing buried-channel PMOS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing buried-channel PMOS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2335922