Method for manufacturing bipolar devices

Details Method for manufacturing bipolar devices Method for manufacturing bipolar devices

1999-12-22

2002-03-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

C438S365000, C438S366000, C257S565000

Reexamination Certificate

active

06362066

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bipolar junction elements like a junction diode or a junction transistor and a method for manufacturing thereof. Especially, the present invention relates to a bipolar transistor and a method for manufacturing the bipolar transistor in which a silicon or a silicon-germanium(SiGe) film is used for a base.
The field of semiconductor with highly advanced technology can be divided into the field of memory, the field of system integrated circuit(IC) which is represented by application specific integrated circuit (ASIC), the field of radio frequency integrated circuit (RFIC) which is essential in wireless communication, and the field of high speed digital & analog integrated circuit for data process. Among these fields of semiconductor, the present invention is especially related to the semiconductor element having high maximum oscillation frequency(f
max
) and high cut-off frequency(f
T
) which are related to the field of RFICs and the high speed digital & analog ICs. As we live in the era where wireless communication is widely used and where its need is increasing explosively, the need of high frequency elements is rising as the quality of communication improves and the markets of higher frequency band providing various communication services and large number of subscribers increase. Also, as the need of super speed information communication network increases in the contemporary society, researches and developments of a high speed transistor are carried on actively. At present, 10 Gbps integrated circuit using high speed transistor about 60 GHz is developed in the usage of optical communications and is at the stage of being commonly used. The silicon homo bipolar junction transistor which includes the silicon base layer formed by ion-implanting a dopant has maximum f
T
of 30 GHz at most. The heterojunction bipolar transistor(HBT) having an epitaxially grown SiGe base layer exhibits maximum f
T
in the range of 50~150 GHz and f
max
of 50~160 GHz.
The SiGe has a narrower energy bandgap(E
g
) than that of the silicon. The energy bandgap difference (&Dgr;E
g
) between the silicon emitter and the SiGe base enhances the current gain exponentially, and the f
T
and the f
max
also increase compared to the homojunction bipolar transistor. Therefore, the impurity doping concentration into the SiGe base can be increased in the margin of exp(&Dgr;E
g
) without degrading the current gain. The base resistance is lowered and consequently the noise figure is lowered. Furthermore, it is possible for power consumption to be lowered because the bias current achieving the same f
T
decreases. In comparison with the base of the transistor formed by ion-implanting in the conventional method, the base formed by the epitaxial growth method can be much thinner to the degree of 200 Å approximately and consequently the cut-off frequency increases. Since the Ge composition in the SiGe base from the emitter side to the collector side ramps up linearly, the electrons transiting to the base accelerate. Therefore, the f
T
and f
max
can be further increased by grading the Ge content. The SiGe HBT is fully process-compatible with silicon devices. Furthermore, it allows to achieve higher f
T
and f
max
than 100 GHz using 0.8~1 &mgr;m of photolithography. This means that, contrast to memory and ASIC getting highly scale-down to 0.18~0.25 &mgr;m, SiGe HBTs can be fabricated by recycling the out-of-date production facilities at the 0. 8~1 &mgr;m level. Therefore, it has good economic value with high output.
2. Description of the Prior Art
There are several registered patents showing related arts of SiGe HBT from IBM in the United States, NEC, Hitachi, and SONY in Japan, TEMIC in Germany, and Electronics and Telecommunications Research Institute(ETRI) in Korea. The structural characteristics and drawbacks of the related arts will be given in the followings.
First, the prior art of NEC in Japan is a kind of the super self-aligned NPN HBT. In this particular transistor, the base layer including SiGe is selectively grown in the device active region and each of the collector-base and the emitter-base junctions is self-aligned. The method for manufacturing this super self-aligned will be described herein below.
In
FIG. 1
a,
a n+ type buried collector
11
is formed by ion-implanting n+ type impurity (dopant) into a p− type silicon substrate
1
. A collector layer
10
is deposited on the resulting structure. A collector sinker
13
which connects the buried collector
11
and a collector semiconductor electrode to be formed afterward is formed by implanting n+ type impurity ions into the region as shown in the figure. A trench is formed by etching the collector layer
10
and the substrate
1
in order to isolate the neighboring transistors electrically. The isolation trench
71
is filled with an insulation material like boron phosphorous silica glass (BPSG). Then, the surface of the isolation trench
71
is planarized by a chemical-mechanical polishing (CMP) of the BSPG so that the surface of the isolation trench
71
becomes a same height with the surface of the collector layer
10
. Form a collector insulation layer
17
with silicon oxide layer, a base semiconductor electrode
23
with p+ type polysilicon film, and an emitter insulation layer
37
with silicon nitride film by sequentially depositing on the substrate
1
where the collector layer
10
and the isolation trench
71
are formed. The collector insulation layer
17
in the region which is planned to be the emitter is exposed by etching the emitter insulation layer
37
and the base semiconductor electrode
23
. Then, by depositing an insulation layer and etching it anisotropically, a first side-wall insulation layer
73
is formed at the inner side-wall of the base semiconductor electrode
23
and the emitter insulation layer
37
. Wet etch the exposed collector insulation layer
17
in order to expose the collector layer
10
beneath the collector insulation layer
17
. Even after the collector layer
10
is exposed, continue the wet etching to form an undercut
27
a
to the pre-determined depth beneath the base semiconductor electrode
23
. The n type impurity ions are added selectively to the intrinsic collector region
15
by ion-implanting to the resulting structure in order to increase the cut-off frequency.
In
FIG. 1
b,
a base layer
20
composed of an undoped SiGe, a p+ SiGe layer, and an undoped Si layer which is supposed to be the emitter
35
later on is grown selectively on the exposed collector layer
10
and beneath the exposed base semiconductor electrode
23
in the undercut
27
a.
Here, a base connecting part
27
i b which is selectively deposited beneath the base semiconductor electrode
23
is a poly-crystalline while the base layer
20
on the collector layer
10
is single crystalline. A silicon film is further selectively grown thereon in order to make sure the connection between the base semiconductor electrode
23
and the base layer
20
. At this step, growth rate of the single crystalline silicon layer on the base layer
20
is controlled to be much slower than that of the poly-crystalline base connecting part
27
b,
so that the thickness variation of the undoped Si layer at the top of the base layer
20
is minimized. The second side-wall insulation layer
75
which covers the first side-wall insulation layer
73
and which contacts with a part of the base layer
20
is formed by depositing the insulation material like a silicon nitride film and by etching it anisotropically. Then, expose the collector sinker
13
by partially opening the collector insulation layer
17
. An n type polysilicon layer is deposited on the resulting structure. Then it is patterned to form an emitter semiconductor electrode
33
on the base layer
20
and a collector semiconductor electrode
13
a
on the collector sinker
13
. Diffuse the impurity in the emitter semiconductor electrode
33
into the undoped Si layer by

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