Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-02-03
2001-06-05
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C435S302100
Reexamination Certificate
active
06242329
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices. The present invention relates more particularly to a method for manufacturing field effect transistors having asymmetric channel doping profiles.
BACKGROUND OF THE INVENTION
Conventional field effect transistors have uniformly doped channel regions. Source/drain regions are implanted and diffused on either side of a polysilicon gate structure. A channel implant step adjusts the threshold voltage of the transistor and produces channel doping which is symmetrically distributed between the source and the drain. Generally, similar processing steps are followed for producing uniformly doped p-channel and n-channel transistors in complementary metal-oxide-semiconductor (CMOS) processes.
Symmetric channel doping has required a tradeoff between maximum drive current, I
Dsat
, and leakage current, I
Doff
. Channel (loping is necessary to limit leakage current in the transistor. Leakage current is the current which flows from source to drain when zero gate to source bias is applied. Minimum leakage current is necessary to limit overall power dissipation in a large scale integrated circuit using many thousands of transistors. However, the channel doping required to limit or control leakage current has the deleterious effect of reducing drive current, which is the current available from the transistor to drive a load. Maximum drive current is necessary to maximize the speed of operation of circuits incorporating the transistor. The tradeoff between leakage current and drive current becomes more severe in deep-submicron transistors, i.e., those with gate lengths below 0.15 &mgr;m.
Recently, asymmetrical channel profiles have been proposed for deep-submicron field effect transistors. Such devices have features which make them advantageous for integrated circuit performance. In particular, asymmetric devices allow for increased drain current (I
Dsat
), which in turn affords higher operational speeds. The asymmetrical channel is achieved by an ion implantation step. This implantation step may replace the implant for the symmetric channel doping or it may be used in addition to that implant.
However, this additional ion implantation step tends to increase manufacturing costs. Additional mask steps are required to define the ion implantation windows for each required transistor orientation. Each additional mask step increases cost and misalignment risk. Misalignment of the masks used for asymmetric channel implant can impair performance of the finished transistor. This is inconsistent with a goal of minimizing masking steps to minimize manufacturing costs.
Accordingly, there is a need for a method for manufacturing field effect transistors having asymmetrical channel profiles which minimizes additional masking steps and manufacturing costs.
SUMMARY
The invention provides a method for asymmetrically doping a field effect transistor. The method includes steps of forming a gate stack on a semiconductor substrate to define a channel region under the gate stack and first and second source/drain regions adjacent to the gate stack. The method further includes steps of masking one of the source/drain regions and implanting dopant at a predetermined tilt angle and rotation angle to dope a portion of the channel region proximate the first source/drain region, thereby asymmetrically doping the field effect transistor.
REFERENCES:
patent: 5258319 (1993-11-01), Inuishi et al.
patent: 5308780 (1994-05-01), Chou et al.
patent: 5429960 (1995-07-01), Hong
patent: 5510279 (1996-04-01), Chien et al.
patent: 5518942 (1996-05-01), Shrivastava
patent: 5935867 (1999-08-01), Alvis et al.
patent: 5960291 (1999-09-01), Krivokapic
patent: 6030871 (2000-02-01), Eitan
patent: 6040208 (2000-03-01), Honeycutt et al.
patent: 6130134 (2000-10-01), Chen
patent: 6140186 (2000-10-01), Lin et al.
Steiner et al., “Minimum-Size Effects in Asymmetric Tilt-Angle -Implanted LDD-WNx-GaAs Mesfet's”. IEEE Transactions on Electron Devices. vol. 38. No. 8. Aug. 1991.*
S. M. Sze,Physics of Semiconductor Devices, Second Edition, published by John Wiley & Sons, pp. 489-90.
Odanaka et al., Potential Design and Transport Property of 0.1 &mgr;m MOSFET with Asymmetric Channel Profile; IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 595-600.
Ohzone et al., Influence of Asymmetric/Symmetric source/Drain Region on Asymmetry and Mismatch of CMOSFET's and Circuit Performance; IEEE Transactions on Electron Devices, vol. 45, No. 2, Feb. 1998, pp. 529-537.
Huster Carl Robert
Riccobene Concetta
Rouse Richard
Wollesen Donald L.
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Loke Steven
Owens Douglas W.
LandOfFree
Method for manufacturing asymmetric channel transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing asymmetric channel transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing asymmetric channel transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473992