Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-11-29
2004-09-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S586000
Reexamination Certificate
active
06790736
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor devices and, more specifically, to a semiconductor device with a polysilicon definition structure and a method for manufacturing the same.
BACKGROUND OF THE INVENTION
The demand for semiconductor devices to be made smaller is ever present because size reduction typically increases speed and performance. Moreover, reduction of the size of components of semiconductor devices can also increase packing density, allowing a manufacturer to produce wafers having more components.
In some conventional semiconductor devices, an emitter contact region is either aligned to a shallow trench or local oxidation on silicon isolation structure or is defined by a photoresist in a non-self-aligned manner. Such methods can make it difficult to control the width of the emitter contact region and difficult to control the distance between the emitter contact region and a base contact region. Furthermore, misalignment during a silicide block process can decrease the reliability of the device.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device and method for manufacturing the same that substantially eliminates or reduces at least some of the disadvantages and problems associated with the previously developed semiconductor devices and methods for manufacturing the same.
In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.
In accordance with another embodiment, a semiconductor device includes a buried layer of a semiconductor substrate. An active region is adjacent at least a portion of the buried layer, and an isolation structure is adjacent at least a portion of the active region. A gate oxide is adjacent at least a portion of the active region. A polysilicon definition structure is adjacent at least a portion of the gate oxide. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The semiconductor device includes an implant region of the emitter contact region, wherein the implant region is self-aligned during formation.
Technical advantages of particular embodiments of the present invention include a semiconductor device with a polysilicon definition structure which enables a manufacturer to more easily control and reduce a width of an emitter contact region of the device. The polysilicon definition structure also enables a manufacturer to reduce the distance between the emitter contact region and a base contact region of the device. Accordingly, such width and distance reductions can increase the unit-to-gain frequency of the semiconductor. Furthermore, manufacturing packing density can be improved since more semiconductor devices may be able to fit on a wafer of a given size.
Another technical advantage of particular embodiments of the present invention includes a semiconductor device with self-aligned implant regions as a result of having a polysilicon definition structure. Furthermore, a silicide block may not be required since the polysilicon definition structure can act as such a block during silicidation. Accordingly, the number of masking steps needed in the manufacturing of the semiconductor device can be reduced which leads to a reduction in time and costs associated with the manufacturing of the device.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some or none of the enumerated advantages.
REFERENCES:
patent: 5717241 (1998-02-01), Malhi et al.
Wolf, S.; Silicon Processing for the VLSI Era vol. 3: The Submicron MOSFET, Sunset Beach, CA, 1995, pp. 634-635.
Brady III W. James
Keagy Rose Alyssa
Lattin Christopher
Niebling John F.
Telecky , Jr. Frederick J.
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