Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-12-03
2004-05-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06737343
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to processes for the formation of an integrated circuits structure and, in particular, to a process for the formation of an integrated circuit that includes metal salicide regions and metal salicide exclusion regions.
2. Description of the Related Art
In Metal-Oxide-Semiconductor (MOS) device manufacturing, selfaligned metal silicide layers (also known as “salicide” layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drains regions, as well as contact resistance. See, for example, Stanley Wolf,
Silicon Processing for the VLSI Era
, Vol. I, 388-399 (Lattice Press, 1986).
FIGS. 1-3
illustrate a conventional process for forming a metal silicide layer over a polysilicon gate, a source region and a drain region of an MOS transistor structure within an integrated circuit (IC). A conventional MOS transistor structure
10
includes a thin gate oxide layer
12
overlying P-type silicon substrate
14
between N-type drain region
16
and N-type source region
18
, both of which are formed in P-type silicon substrate
14
. A conventional MOS transistor structure
10
also includes a polysilicon gate
20
overlying thin gate oxide layer
12
, as well as field oxide regions
22
, which isolate MOS transistor structure
10
from neighboring semiconductor device structures (not shown). Gate sidewall spacers
24
, typically formed of silicon dioxide and/or silicon nitride, are disposed on the lateral edges of polysilicon gate
20
and thin gate oxide layer
12
.
In a conventional metal silicide formation process, a metal layer
28
is deposited over the surface of MOS transistor structure
10
, as illustrated in FIG.
2
. Metal layer
28
is ordinarily deposited by a multi-directional evaporative or sputtering-based physical vapor deposition (PVD) process or a multi-directional chemical vapor deposition (CVD) process and is, therefore, of essentially uniform thickness over the entire surface of MOS transistor structure
10
.
Wherever metal layer
28
is in contact with silicon surfaces (i.e. source region
18
, drain region
16
and the polysilicon surface of polysilicon gate
20
) the metal is reacted to form a metal silicide layer. The reaction conditions, such as temperature and gaseous ambient, employed for the metal silicide layer formation are selected to foster the reaction of the metal layer with silicon surfaces while impeding the reaction of the metal layer with silicon dioxide or silicon nitride surfaces (i.e. the gate sidewall spacers and field oxide regions).
A selective etch is then used to remove unreacted metal from the surface of the gate sidewall spacers and field oxide regions, as well as any unreacted metal residue still remaining above the source region, drain region and polysilicon gate. The etch is “selective” since it does not remove the metal silicide layer that was formed on the surface of the silicon and polysilicon regions. The result, illustrated in
FIG. 3
, is a metal silicide layer
32
on the surface of drain region
16
, a metal silicide layer
34
on the surface of source region
18
and a metal silicide layer
36
on the surface of polysilicon gate
20
.
It can be desireable to form integrated circuits that include both MOS transistors structures with metal salicide layers (i.e., metal salicide regions) and MOS transistor structures without metal salicide layers (i.e., metal salicide exclusion regions). For example, it is often beneficial to form input/output (I/O) MOS transistor structures without metal salicide layers in order to provide a relatively high resistance I/O path for electrostatic discharge (ESD) protection.
Conventional processes for the formation of IC structures with metal salicide regions and metal salicide exclusion regions involve a series of steps that form a layer of silicon dioxide over MOS transistor structures where metal salicide exclusion regions are to be formed, prior to the deposition of a metal layer. This series of steps includes depositing a silicon dioxide layer on an integrated circuit structure, forming a photoresist masking layer on the silicon dioxide layer, removing the silicon dioxide layer from the MOS transistor structures where metal salicide regions are to be formed, and then stripping the photoresist masking layer. This series of steps is followed by the deposition of a metal layer and the formation of metal salicide regions.
A drawback of conventional processes for the formation of IC structures with metal salicide regions and metal salicide exclusion regions is the potential for the step of removing the silicon dioxide layer to damage the MOS transistor structures where metal salicide regions are to be formed. For example, if the silicon dioxide layer is removed from the MOS transistor structures where metal salicide regions are to be formed using an HF acid or buffered oxide etchant (BOE), then there is a potential for the HF acid and BOE to attack gate sidewall spacers formed of silicon dioxide. In addition, the conventional processes are relatively complicated and requires many steps since they involve the deposition of a silicon dioxide layer, the formation of a masking layer, the removal of the silicon dioxide layer and the stripping of the photoresist masking layer.
Still needed in the field is a process for manufacturing an integrated circuit structure with a metal salicide region(s) and a metal salicide exclusion region(s) that is simple, requires a minimum number of steps, does not subject MOS transistor structures where metal salicide regions are to be formed to damage by a silicon dioxide layer removal process step, and can be controlled to produce metal salicide regions with predetermined attributes (e.g., sheet resistance).
SUMMARY OF THE INVENTION
The invention is a process for forming metal salicide regions and metal salicide exclusion regions during integrated circuit (IC) manufacturing. The process requires a minimum number of steps, does not subject MOS transistor structures to a silicon dioxide removal process step, is compatible with standard MOS processing techniques and provides for the formation of metal salicide regions (such as source regions, drain regions or polysilicon gates) on predetermined MOS transistor structures, while also providing for the formation of metal salicide exclusion regions on other predetermined MOS transistor structures in an IC.
Processes according to the present invention include first providing an IC structure that includes a plurality of MOS transistor structures with exposed silicon surfaces (such as source regions, drain regions, and polysilicon gates). A metal layer (e.g., cobalt, titanium , tantalum, nickel or molybdenum) is then deposited over the IC structure in a controlled manner. If a cobalt layer is used as the metal layer, then a capping layer (e.g., titanium or titanium nitride) is subsequently deposited thereon. A photoresist masking layer is then formed on those MOS transistor structures where metal salicide regions are to be formed, followed by removal of the metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed. Next, the metal layer (as well as the capping layer, if any) is removed from those MOS transistor structures where metal salicide exclusion regions are to be formed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed. Then, metal (in those portions of the metal layer not previously removed) in contact with the exposed silicon surfaces is reacted to form metal salicide regions. By appropriately controlling parameters of the metal layer deposition step, the metal to be reacted (to produce metal salicide) and the metal salicide resulting from the reaction are caused to have desired properties. For example, where the metal salicide formation step is a step in forming a polysilicon interconnection, the metal deposition step can be performed in a manner that results in
Girard & Equitz LLP
Hoang Quoc
National Semiconductor Corporation
Nelms David
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