Method for manufacturing a trench capacitor

Details Method for manufacturing a trench capacitor Method for manufacturing a trench capacitor

2001-03-19

2003-03-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S392000, C438S243000, C438S249000

Reexamination Certificate

active

06528384

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for manufacturing a trench capacitor, and in particular to a method for manufacturing a trench capacitor in a semiconductor memory cell of an integrated circuit.
Integrated circuits having such a semiconductor memory cell are, for example, random access memories (RAM, random access memory), dynamic memories (DRAM, dynamic random access memory), synchronous dynamic memories (SDRAM, synchronous DRAM), static memories (SRAM, static random access memory), read-only memories (ROM) or other memory circuits such as programmable logic fields (PLA, programmable logic array), user-specific integrated circuits (ASIC, application-specific IC) and the like.
In order to explain the invention, a conventional method for manufacturing a trench capacitor in a dynamic semiconductor memory cell of a dynamic memory DRAM will be described below.
FIG. 1
shows a conventional trench capacitor such as is used in particular in a DRAM semiconductor memory cell, and is described, for example, in U.S. Pat. No. 5,945,704. Such a DRAM semiconductor memory cell is formed essentially of a capacitor
160
, which is formed in a substrate
101
. The substrate
101
is slightly doped with, for example, p-type dopants such as boron (B). A trench is usually filled with polysilicon
161
, which is highly n
+
-type doped with, for example, arsenic (As) or phosphorus (P). A buried plate
165
which is doped with, for example, arsenic (As) is located in the substrate
101
at a lower region of the trench. The arsenic (As) or, generally speaking, the dopant is usually diffused into the silicon substrate
101
from a dopant source such as an arsenic silicate glass ASG which is formed on the side walls of the trench. The polysilicon
161
and the buried plate
165
serve here as electrodes of the capacitor, a dielectric layer
165
separating the electrodes of the capacitor.
The DRAM semiconductor memory cell according to
FIG. 1
also has a field-effect transistor
110
. The transistor has a gate
112
and diffusion zones
113
and
114
. The diffusion zones, which are spaced apart from one another by a channel
117
, are usually formed by the implantation of dopants such as phosphorus (P). A contact diffusion zone
125
connects the capacitor
160
to the transistor
110
here.
An insulating collar
168
is formed on an upper section or upper region of the trench. The insulating collar
168
prevents a leakage current from the contact diffusion zone
125
to the buried plate
165
. Such a leakage current is undesirable, in particular in memory circuits, because it reduces the charge holding time or retention time of a semiconductor memory cell.
According to
FIG. 1
, the conventional semiconductor memory cell with trench capacitor also has a buried well or layer
170
, the peak concentration of the dopants in the buried n-type well being located approximately at the lower end of the insulating collar
168
. The buried well or layer
170
serves essentially to connect the buried plates
165
of a multiplicity of adjacent DRAM semiconductor memory cells or capacitors
160
in the semiconductor substrate
101
.
Activation of the transistor
110
by applying a suitable voltage to the gate
112
permits essentially access to the trench capacitor, the gate
112
being usually connected to a word line
120
, and the diffusion zone
113
being usually connected to a bit line
185
in the DRAM field. The bit line
185
is separated from the diffusion zone
113
here through the use of a dielectric insulating layer
189
, and electrically connected via a contact
183
.
In addition, in order to insulate a respective semiconductor memory cell with an associated trench capacitor from adjacent cells, a shallow trench insulation (STI)
180
is formed on the surface of the semiconductor substrate
101
. According to
FIG. 1
, it is possible to form, for example, the word line
120
above the trench so that it is insulated by the shallow trench insulation (STI), resulting in a so-called folded bit line architecture.
In this way, a semiconductor memory cell is obtained which has a minimum space requirement and is thus very much suited for highly integrated circuits.
According to U.S. Pat. No. 5,945,704, a number of methods is used, in particular for forming the buried plate
165
. In addition to ion implantation of arsenic or phosphorus, plasma doping or plasma immersion ion implantation, gas phase doping with AsH
3
or PH
3
is also possible.
However, what is disadvantageous, in particular with conventional gas phase doping, which is usually carried out at a pressure of several 100 Torr (13.3 kPascal), is that the silicon begins to flow, as a result of which the silicon patterns are deformed, and moreover the insulating collar does not constitute a sufficient barrier for the diffusion with respect to the dopants. On the other hand, the use of ion implantation, plasma doping, plasma immersion ion implantation or a doping source in the trench significantly complicates the manufacturing process, as a result of which the manufacturing costs are increased and the yield is reduced.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for manufacturing a trench capacitor which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which allows to produce the trench capacitors and the respective devices having such trench capacitors with a high yield and in a particularly simple and cost-effective way.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for manufacturing a trench capacitor, the method includes the steps of:
(a) providing a substrate;
(b) forming a trench with a lower region and an upper region in the substrate;
(c) filling the lower region of the trench with a first filler material;
(d) forming an insulation collar in the upper region of the trench;
(e) removing the first filler material from the lower region of the trench;
(f) forming a buried plate as a first capacitor plate in the substrate such that the buried plate is disposed adjacent to the lower region of the trench and using a low-pressure gas phase doping for forming the buried plate;
(g) forming a dielectric layer as a capacitor dielectric lining the lower region of the trench and an inner side of the insulation collar; and
(h) filling the trench with a conductive second filler material as a second capacitor plate.
The method according to the invention can reliably prevent a diffusion of dopants (for example arsenic or phosphorus) through the insulating collar, in particular in comparison with conventional gas phase doping methods, by, in particular, forming the buried plate with a low-pressure gas phase doping, as a result of which a leakage current is greatly reduced and, respectively, a charge holding time (retention time) is significantly improved. The term low-pressure gas phase doping is to be understood as a gas phase doping at a pressure of less than several hundred Torr as is used in the prior art. At the same time, significantly higher dopant concentrations are obtained in the lower region of the trench, as a result of which the capacitance of the capacitor can be significantly improved due to a reduced space charge region (depletion region). As a result, a trench capacitor with a sufficient capacitance is obtained which is in particular suitable for further technology “shrinks.”
The buried plate is preferably formed at a pressure of 66 Pascal to 200 Pascal (0.5 to 1.5 Torr) and at a temperature of 750° C. to 1050° C. using AsH
3
or PH
3
in a carrier gas composed of H
2
or He. A further cost saving is obtained by virtue of the simplification of the process in particular in comparison with an ASG deposition process for forming the buried plate with a subsequent high temperature step for diffusing out the dopants. Moreover, the potential risk with such a low pressure and temperature is reduced significantly in comparison with conve

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