Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2007-04-10
2007-04-10
Schillinger, Laura M. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S079000
Reexamination Certificate
active
11233038
ABSTRACT:
A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads, under the zero thickness portion, are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed but the portions of the passivation layer under the thick portions of the photoresist pattern is not removed. Then, a plurality of pixel electrodes, redundant gate pads and redundant data pads are formed.
REFERENCES:
patent: 4865945 (1989-09-01), Noguchi et al.
patent: 5882827 (1999-03-01), Nakao
patent: 6133977 (2000-10-01), Lee et al.
patent: 6215541 (2001-04-01), Song et al.
patent: 6255130 (2001-07-01), Kim
patent: 6256077 (2001-07-01), Baek
patent: 6287899 (2001-09-01), Park et al.
patent: 6289899 (2001-09-01), Park et al.
patent: 6300152 (2001-10-01), Kim
patent: 6335211 (2002-01-01), Lee
patent: 6335276 (2002-01-01), Park et al.
patent: 6429057 (2002-08-01), Hong et al.
patent: 6524876 (2003-02-01), Baek et al.
patent: 6531392 (2003-03-01), Song et al.
patent: 6611309 (2003-08-01), Park et al.
patent: 6642074 (2003-11-01), Hong et al.
patent: 6678018 (2004-01-01), Park et al.
patent: 6759281 (2004-07-01), Kim et al.
patent: 6806937 (2004-10-01), Park et al.
patent: 7098480 (2006-08-01), Kim et al.
patent: 7102168 (2006-09-01), Rhee et al.
patent: 2001/0046016 (2001-11-01), Park et al.
patent: 2003/0085404 (2003-05-01), Kim et al.
patent: 2003/0133067 (2003-07-01), Park et al.
patent: 2003/0136971 (2003-07-01), Rhee et al.
patent: 2005/0082536 (2005-04-01), Park et al.
patent: 2006/0011921 (2006-01-01), Park et al.
patent: 2006/0157712 (2006-07-01), Kim et al.
patent: 62-281428 (1987-12-01), None
Baek Bum-Ki
Park Woon-Yong
Samsung Electronics Co,. Ltd.
Schillinger Laura M.
LandOfFree
Method for manufacturing a thin film transistor array panel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a thin film transistor array panel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a thin film transistor array panel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3754427