Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-12-08
2002-05-14
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S181000, C438S195000
Reexamination Certificate
active
06387738
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor having a transparent three-layered structure that can be simultaneously used as a source electrode, a drain electrode and a pixel electrode.
2. Description of the Prior Art
In a flat panel display, thin film transistors can improve the display quality by driving individual pixels. Thus, they have been widely used as on/off switching elements of pixels in a flat display device such as an active matrix liquid crystal displays. The thin film transistors used for that purpose should be able to withstand high voltages and have a high ratio of on-currents to off-currents. Also, when current is applied, the thin film transistors are affected by the resistance between metal and a polycrystalline silicon thin film and the contact resistance between layers.
Thin film transistors have two types. One is an amorphous silicon transistor and the other is a polycrystalline silicon transistors. The polycrystalline silicon transistor is favored more than the amorphous silicon transistor because of its high electron mobility and its reliability. However, the amorphous silicon transistors are practically used since layers of the polycrystalline silicon transistor should be formed at a high temperature atmosphere.
Most recently, a technology of easily forming the polycrystalline silicon on a cheap glass substrate by using the excimer laser equipment has been developed, drawing more attention to the polycrystalline silicon thin film transistors.
In the polycrystalline silicon transistor, a coplanar structure is preferred. The coplanar structure has electrodes, for instance, gate, source and drain electrodes arranged at both sides of a semiconductor. The coplanar structure is able to minimize the device size and is convenient to realize CMOS having PMOS and NMOS.
FIG. 1
illustrates a thin film transistor of the conventional coplanar structure.
In the drawing, a buffer layer
4
is formed on an upper surface of a substrate
2
by depositing an oxide layer. An active layer
6
of amorphous silicon is deposited and crystallized at a predetermined portion of the buffer layer
4
.
After crystalizing the active layer
6
, an insulating layer
8
is formed on the active layer
6
. A gate metal layer is deposited on the insulating layer
8
. The gate metal layer is patterned by a photolithography process to form a gate electrode
10
.
Next, a contact layer
12
is formed at both edges of the active layer
6
by a high concentration ion doping method, thereby leaving an offset region
14
between the contact layers
12
. A lightly doped drain (LDD) region is formed by doping the offset region
14
lightly using the gate electrode
10
as a mask.
Finally, an interlayer insulating layer
15
is deposited on an upper surface of the gate electrode
10
. And then a contact hole that exposes the contact layer
12
is formed. Hereto, a source electrode or a drain electrode
16
is deposited and then patterned thereby completing a desired thin film transistor structure.
In the manufacturing process of the conventional thin film transistors as described above, the photolithography process should be conducted at the steps of defining the active layer; forming the gate electrode; doping n+; doping n−; doping p+; forming the contact hole; and forming the source/drain electrodes, as well as at subsequent steps of forming a via hole; forming a pixel electrode; and doping p channel.
However, as is well known, since the photolithography process comprises various steps of photoresist coating; mask-exposing; and developing/etching, the increased number of process steps may significantly lower the productivity and degrade the quality of the product. Accordingly, numerous suggestions to reduce the number of processes for manufacturing the thin film transistor have been made. Among the suggestions, the source and the drain electrodes are formed from the contact layer by filling an ITO layer, which simplifies the manufacturing process. However, it causes a problem of the contact resistance between the polycrystalline silicon thin film and the ITO layer at a boundary of the contact layer doped with high density.
Further, an RC delay may happen in a high resolution or a large size panel when a data line is used by the ITO layer that has a higher resistance than any of conventional metal electrode.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film transistor that can reduce the number of process steps by using a three-layered thin film as a source electrode, a drain electrode and a pixel electrode simultaneously, and that can also lower the contact resistance between layers.
In order to accomplish the foregoing object, the present invention leaves the photoresist layer on the gate electrode after patterning the gate electrode. The photoresist layer is then reflowed by heating to cover the side edges of the gate electrode. Using the reflowed photoresist covering the side edges of the gate electrode, the substrate is doped with highly concentrated ions to form a contact layer. Then, after removing the reflowed photoresist layer, the substrate is doped with lightly concentrated ions to form a lightly doped drain. The interlayer insulating layer is deposited and a contact hole is formed. A three-layered thin film of a first metal layer, an indium tin oxide (ITO) layer, a second metal layer is deposited and a data line is formed on the second metal layer by an electroplating method.
In the present invention, the first metal layer is below 100 Å thick and preferably below 50 Å. The ITO layer is below 1000 Å thick and preferably below 600 Å. In addition, the second metal layer is below 100 Å thick and preferably below 50 Å.
A metal selected from the group consisting of Ag, Al and Au having low electric resistance, or their alloy can be used for the metal layers.
Since the thin film transistor of the present invention uses the three-layered thin film for all of the source, drain and pixel electrodes, patterning processes of forming a via hole and forming a pixel electrode can be omitted. Further, the present invention lowers the contact resistance between the ITO layer and the polycrystalline silicon thin film.
REFERENCES:
patent: 5793058 (1998-08-01), Han et al.
patent: 5885859 (1999-03-01), Han et al.
patent: 5920085 (1999-07-01), Han et al.
patent: 6081308 (2000-06-01), Jeong et al.
patent: 6310670 (2001-10-01), Lee
Christianson Keith
McGuireWoods LLP
Samsung SDI & Co., Ltd.
Schillinger Laura M
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