Method for manufacturing a stacked capacitor DRAM cell

Details Method for manufacturing a stacked capacitor DRAM cell Method for manufacturing a stacked capacitor DRAM cell

1990-10-04

1992-05-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437233, 437919, 437981, H01

Patent

active

051148730

ABSTRACT:
The method comprises the steps of: forming the transistor on a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask; horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film; vertically etching the second conductive layer, first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the third conductive layer and second insulating film by applying the etching mask of the second conductive layer; additionally depositing the third conductive layer. The method attains larger effective capacitance in which a plate electrode layer surrounds even the lower surface of a storage electrode layer of the stack capacitor without using any extra mask.

REFERENCES:
patent: 4742018 (1988-03-01), Kimura et al.
patent: 4910566 (1990-03-01), Ema
patent: 4961165 (1990-10-01), Ema

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