Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2007-04-03
2007-04-03
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S033000, C438S068000, C438S106000, C438S109000, C438S110000, C438S113000, C438S458000, C438S460000, C438S617000, C257S686000, C257S777000, C257S784000
Reexamination Certificate
active
10701742
ABSTRACT:
A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.
REFERENCES:
patent: 4567643 (1986-02-01), Droguet et al.
patent: 5012323 (1991-04-01), Farnworth
patent: 5953216 (1999-09-01), Farnworth et al.
patent: 6229217 (2001-05-01), Fukui et al.
patent: 6326698 (2001-12-01), Akram
patent: 6352879 (2002-03-01), Fukui et al.
patent: 6495442 (2002-12-01), Lin et al.
patent: 6531784 (2003-03-01), Shim et al.
patent: 6538313 (2003-03-01), Smith
patent: 6541846 (2003-04-01), Vaiyapuri
patent: 6607940 (2003-08-01), Yasunaga
patent: 6642610 (2003-11-01), Park et al.
patent: 6683385 (2004-01-01), Tsai et al.
patent: 6700186 (2004-03-01), Yasunaga et al.
patent: 6709893 (2004-03-01), Moden et al.
patent: 6815746 (2004-11-01), Suzuki et al.
patent: 6841881 (2005-01-01), Katagiri et al.
patent: 7071574 (2006-07-01), Nojiri et al.
patent: 2002/0027273 (2002-03-01), Huang
patent: 2002/0109216 (2002-08-01), Matsuzaki et al.
patent: 2002/0197769 (2002-12-01), Choi, III
patent: 2003/0006492 (2003-01-01), Ogasawara et al.
patent: 2003/0020151 (2003-01-01), Chen et al.
patent: 2003/0025188 (2003-02-01), Farnworth et al.
patent: 2003/0032263 (2003-02-01), Nagao et al.
patent: 2003/0049882 (2003-03-01), Yin et al.
patent: 2003/0062628 (2003-04-01), Lee et al.
patent: 2003/0094683 (2003-05-01), Poo et al.
patent: 2003/0099097 (2003-05-01), Mok et al.
patent: 2003/0153122 (2003-08-01), Brooks
patent: 2003/0160312 (2003-08-01), Lo et al.
patent: 2003/0203537 (2003-10-01), Koopmans
patent: 8250651 (1996-09-01), None
patent: 11135714 (1999-05-01), None
patent: 2002-261233 (2002-09-01), None
Hetzel Wolfgang
Thomas Jochen
Wennemuth Ingo
Infineon - Technologies AG
Jr. Carl Whitehead
Mitchell James M.
Slater & Matsil L.L.P.
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