Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-26
2004-10-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S658000, C438S648000, C438S683000, C438S653000
Reexamination Certificate
active
06800553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device capable of forming a uniform silicide layer with low resistance in a highly-integrated semiconductor device.
2. Description of the Prior Arts
As is generally known, a silicide process is Performed to reduce sheet resistance on the surface of semiconductor device. For example, a silicide layer is additionally formed on the surface of gate electrode and source/drain regions to reduce RC delay time of MOS transistor.
Tungsten silicide (WSi
2
), titanium silicide (TiSi
2
) and cobalt silicide (CoSi
2
) may be mentioned as examples of the silicide used in the semiconductor device. Especially, titanium silicie (hereinafter, referred to as Ti silicide) is widely used in junctions to improve the speed of signal process in a highly-integrated semiconductor device.
A conventional method for manufacturing a silicide layer of semiconductor device will be described in more detail with reference to accompanying drawings.
Referring to
FIG. 1
, a field oxide layer
12
is formed on a silicon substrate
10
to define an active region and an inactive region of semiconductor device.
And, a gate oxide layer
13
and a doped polysilicon layer are sequentially deposited on the active region of the silicon substrate
10
and patterned to form a gate electrode
14
.
Subsequently, ion impurities are implanted into source/drain regions of the substrate in low concentration, thereby forming a LDD (Lightly Doped Drain) region
16
and then, a spacer
18
is formed on the side of the gate electrode
14
with a silicon oxide layer (SiO2) or a silicon nitride layer (Si3N4).
Then, source/drain regions
20
are formed by ion-implanting impurities in high concentration into the resulting structure having the spacer
18
.
Referring to
FIG. 2
, a Ti layer
22
and a TiN layer
24
are deposited on the entire surface of the resulting structure with metal and then, a RTP (Rapid Thermal Process) is performed.
Therefore, as shown in
FIG. 3
, silicon on the gate electrode
14
and source/drain regions
20
generates silicide reaction with the Ti layer
22
and the TiN layer
24
by the RTP, thereby forming a Ti silicide layer (TiSix)
26
on the surfaces thereof.
Then, unreacted Ti layer
22
and the TiN layer
24
are removed to prevent Ti silicide layers
26
a
,
26
b
of the gate electrode
14
and source/drain regions
20
from electrically being connected to each other.
As described above, it is possible to degrade the sheet resistance by the Ti silicide layer
26
a
on the gate electrode
14
and the Ti silicide layer
26
b
on the source/drain regions
20
. Therefore, contact resistance is lowered in manufacturing wiring in contact with the gate electrode
14
and the source/drain regions
20
.
However, it becomes difficult to form a uniform silicide layer when a line width of gate electrode is reduced by a design rule in a highly-integrated semiconductor device. This is because when stable silicide C
54
phase is formed by phase transition of unstable silicide C
49
phase, there is no nucleation space of C
54
phase on C
49
phase due to the reduced line width of gate electrode, thereby forming a dense Ti silicide layer having a irregular and discontinuous C
54
phase on one nucleation site.
Therefore, according to the conventional method for manufacturing a silicide, irregular silicide layer is formed by a reduced line width of gate electrode, thereby increasing silicide resistance on the gate electrode and source/drain regions and generating leakage current which result in degradation of device properties.
SUMMARY OF THE INVENTION
Therefore, the present invention has been proposed to solve the above problems and it is the primary objective of the present invention to provide a method for manufacturing a silicide layer of semiconductor device having uniform silicde layers in a later thermal treatment process.
In order to accomplish the above objectives, a method of forming a silicde layer of semiconductor device according to the present invention comprises the steps of: depositing a lower metal layer on the surface of semiconductor substrate and then, performing plasma treatment; and depositing an upper metal layer on the plasma-treated lower metal layer and then, performing a thermal treatment process, thereby forming a silicide layer on the surface of semiconductor substrate.
And, a method for forming a silicide of semiconductor device according to the present invention comprises the steps of: forming a gate electrode of polysilicon layer on the upper part of semiconductor substrate; forming a spacer of insulation material on the sidewall of gate electrode; forming source/drain regions by ion-implanting impurities in both sides of substrate of gate electrode; depositing a lower metal layer on the entire surface of resulting structure and then, performing a plasma treatment with Ar or N2 gas; and depositing an upper metal layer on the upper part of lower metal layer and then, performing first and second thermal treatment processes, thereby removing a metal layer unreacted with silicon and forming a silicide layer on the upper part of gate electrode and source/drain.
REFERENCES:
patent: 6110821 (2000-08-01), Kohara et al.
patent: 6150249 (2000-11-01), Lee et al.
patent: 6287966 (2001-09-01), Liu et al.
patent: 6482737 (2002-11-01), Hamanaka
patent: 6727165 (2004-04-01), Puchner et al.
Jung Byung Hyun
Kim Hyoung Yoon
Anya Igwe U.
Dongbu Electronics Co., Ltd
Keefer Timothy J
Seyfarth Shaw LLP
Smith Matthew
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