Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-01-14
2002-02-19
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S113000, C438S114000, C438S462000, C438S977000, C438S459000
Reexamination Certificate
active
06348363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit packages and manufacture of intergrated circuit packages and more particularly to preventing electrical shorts that result from bonding wires contacting the edge of a semiconductor chip.
2. Description of the Related Art
A typical goal in manufacture of electronic appliances is to make the electronic appliances small and thin. To meet this goal, the integrated circuits in thr electronic appliances also need to be small and thin. Accordingly, high-density integration, which provides smaller semiconductor chips, and efficient packaging, which provides smaller IC packages, have become very important for the devices in electronic appliances. In the computer filed, semiconductor chips need to be relatively large to accommodate the required capabilities and the large numbers of circuit elements in devices, such as RAMs (Random Access Memories) and Flash memories. Accordingly, smaller packages for the chips have been studied.
One way to reduce chip size is to form a center pad type semiconductor chip. Generally, a center pad type semiconductor chip is smaller than an edge pad type semiconductor chip that contains the same circuitry. Accordingly, many integrated circuit manufacturers make semiconductor chips of the center pad type to obtain more chips per wafer.
One of the packages recently developed is the ball grid array (BGA) package. The BGA package has advantages of requiring a small mounting area on a motherboard and providing superior electrical characteristics when compared to a plastic package. In a BGA package, a printed circuit board is used instead of the lead frame common to plastic packages. A semiconductor chip attaches to one surface of the circuit board. On the opposite surface of the circuit board are solder balls that act as external terminals for direct attachment to a motherboard. The BGA package has the advantage of a high mounting density on the motherboard. However, bonding wires in a package containing a center pad type semiconductor chip extend across part of the semiconductor chip and then down to a lead frame or printed circuit board on which the semiconductor chip is mounted. These bonding wires can sag or otherwise contact the edge of an active surface of the semiconductor chip and create electrical shorts.
FIG. 1
shows a cross-sectional view of a known BGA package
100
.
FIG. 2
shows a cross-sectional view of a wafer being separated into semiconductor chips
10
, one of which is in the BGA package of FIG.
1
. As shown in
FIGS. 1 and 2
, the BGA package
100
includes the semiconductor chip
10
that is mounted on an upper surface of a substrate
20
. Bonding wires
50
electrically connect a pad
12
on the semiconductor chip
10
to the substrate
20
. A molding resin encapsulates an upper surface of the substrate
20
including the semiconductor chip
10
and the bonding wire
50
, thereby forming a resin encapsulation portion
30
. Solder balls
40
on a lower surface of the substrate
20
connect to the semiconductor chip
10
via conductive patterns
24
and conductive vias
26
.
The substrate
20
is a printed circuit board including a substrate body
22
. The conductive patterns
24
include a top wiring pattern
23
on the upper surface of the substrate body
22
and and a bottom wiring pattern
25
formed on the lower surface of the substrate body
22
. The bonding wires
50
electrically connect the bonding pads
12
to the top wiring pattern
23
. Conductive vias
26
electrically connect to the top wiring pattern
23
to the bottom wiring pattern
25
on which the solder balls
40
reside.
The semiconductor chip
10
is of the center pad type and has the bonding pads
12
in a central portion of an active area. The semiconductor chip
10
also includes a silicon substrate
90
, a nitride layer
14
, and a polyimide layer
16
. Integrated circuit elements reside in and on silicon substrate
90
, and nitride layer
14
as a non-active passivation layer protects the integrated circuits and pads
12
. Polyimide layer
16
helps resist collection of an electrostatic charge on the nitride layer
14
and damage from alpha rays.
As shown in
FIG. 2
, scribe areas
82
separate the semiconductor chips formed in a wafer
80
. A diamond cutter
60
cuts wafer
80
along the scribe area
82
and separates individual semiconductor chips
10
. To facilitate cutting of the wafer
80
, polyimide layers are absent from the scribe areas
82
. Otherwise, the polyimide can stick to cutter
60
and cause chipping of the wafer
80
.
Returning to
FIG. 1
, the length of a bonding wire
50
that connects a pad
12
and the top wiring pattern
23
of the substrate
20
is longer than that of a bonding wire in packaging for a semiconductor chip of the edge pad type. Further, the bonding wire
50
is typically at a low height above the chip
10
to reduce the thickness of the semiconductor package
100
. Accordingly, the bonding wire
50
may contact the edge
18
of the active area of the semiconductor chip
10
.
As noted above, the polyimide layer
16
is missing from the edge of the active area of the semiconductor chip
10
, and a nitride layer
14
is exposed. When the bonding wire sags or otherwise contacts the edge
18
of semiconductor chip
10
, the nitride layer
14
may insulate the bonding wire
50
from underlying integrated circuits, but electrical shorts can result because the nitride layer is thin and may be chipped. The electrical shorts are often a consequence of the mechanical cutting of a wafer. A cutting process preferably cuts the nitride layer
14
to form a very smooth surface, and chipping during the cutting process can expose the edge of an active surface in the silicon substrate
90
below the nitride layer
14
and allow shorts with the bonding wire
50
.
Increasing the height of the bonding wire to avoid contact with the edge of the semiconductor chip avoids electrical shorts, but increasing the height of the bonding wire also increases the thickness of the semiconductor package. Additionally, larger semiconductor chips have longer distance from the pads to the edge in the semiconductor chip, and the thickness of the packages must increase in proportion to the size of the chip. Otherwise the probability of the bonding wire contacting the edge of the semiconductor chip increases, and the problem of electrical shorts arises.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a semiconductor package has an insulating region at the edge of the active area of the semiconductor chip to avoid electrical shorts when bonding wires contact the edge of the active area of the semiconductor chip.
In one embodiment of the invention, a semiconductor package includes a semiconductor chip, a substrate, and a resin encapsulation portion. The semiconductor chip includes a silicon substrate having an active area containing integrated circuits and a plurality of pads. The pads electrically connect to the integrated circuits and are along a center portion of the active area. A non-active layer overlies the active area except for the pads, and a polyimide layer is on the non-active layer. The polyimide layer helps prevent damage resulting from electrical shorts or alpha rays. A surface of the semiconductor chip, which is the opposite the active area of the semiconductor chip, attaches to an upper surface of the substrate. One or more bonding wires electrically connect the pads of the semiconductor chip to the substrate. The resin encapsulation portion encapsulates the semiconductor chip and bonding wires on the upper surface of the substrate. External terminals are on the lower surface of the substrate and electrically connected to the semiconductor chip. At the edge of the substrate, the boding wire contacts with the polyimide layer, thereby preventing electrical shorts between the bonding wire and the silicon substrate.
In another embodiment of the present invention, a semiconductor package includes a semiconductor chip, a
Choi Hee Kook
Chung Myung Kee
Lee San Yeop
Jones Josetta I.
Niebling John F.
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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