Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-28
2002-04-23
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S626000, C438S700000, C438S723000
Reexamination Certificate
active
06376357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the semiconductor device, and more specifically to a semiconductor device having an insulation film between wiring and a method of manufacturing this type of semiconductor device.
2. Description of Related Art
Recently, along with the shrinking of the design rule for semiconductor devices, the spacing between wiring has become more and more narrow, to the extent that the capacitance between adjacent wirings has become a large problem.
Because of this, there is a desire to achieve a low dielectric constant in interlayer insulation films, and one method of achieving this low dielectric constant that has been proposed is that of forming a void in an insulation film previously used, in order to reduce the dielectric constant.
For example, in the Japanese Unexamined Patent Publication No. 2-86146, as shown in the cross-sectional view of
FIG. 5
, there is a proposal of a method of using the shape of the overhang at the end of a wiring when growing the insulation film
34
a
to make a void
35
between the wirings (
33
a
,
33
b
, and
33
c
).
In the Japanese Unexamined Patent Publication No. 4-207055, as shown in the cross-sectional view of
FIG. 6
, there is a proposal of a method of burying an insulation film
54
which can be selectively etched between the wirings
44
, and then performing isotropic etching from an aperture
56
to selectively etch the buried insulation film
54
, thereby forming a void
50
.
As the same type of technology, there is the example of the Japanese Unexamined Patent Publication No. 5-21617 in which, as shown in the process cross-sectional views of FIG. 7(
e
) through FIG. 7(
g
), there is a proposal of a method of selectively removing an insulation film 65, which is buried between the wirings 63
a
and 63
b
, starting at the small aperture 66
a
, so as to form the void 68
a
, thereby reducing the capacitance between the wirings.
FIG. 7(
h
) shows the configuration of another embodiment that is presented in the above-noted Japanese Unexamined Patent Publication No. 5-21617.
The above-noted prior art, however, has the following problems.
(1) In the method in the past of making a void between wirings, as described in the Japanese Unexamined Patent Publication No. 2-86146, which was described with reference to
FIG. 5
, because the shape of the overhang at a wiring end during interlayer insulation film, it is only possible to form a void when the wiring-to-wiring spacing is suitable for application of a formation of a void using the overhang.
Additionally, the size and the shape of the void is dependent in the above-noted method upon the wiring-to-wiring spacing and the cross-sectional shape of the wirings, leading to the problem of variations in the effect of reducing the capacitance.
Additionally, because the shape of the overhang of the insulation film is used, there is an increase in the step after the formation of the interlayer insulation film, making it difficult to achieve flattening in downstream processes, thereby hindering the achievement of smaller design rules.
(2) In the above-noted methods noted in the Japanese Unexamined Patent Publication Nos. 4-207055 and 5-21617, the method of making a void is that of performing selective etching from a small aperture in order to remove an insulation film that has a high etching rate and that is buried between wirings, it is necessary to add a photoresist process in order to form the aperture, this resulting in a major increase in the number of process steps.
Additionally, because the aperture is small in comparison with the size of the void, when using wet etching to form the void by etching, it is difficult to reliably remove the etching fluid, this leading to failures in downstream processes and to corrosion of wirings, which bring about a reduction in reliability.
Additionally, in order to establish mechanical strength in an LSI device with multilevel wiring, it is necessary to have wiring which does not have a void therebetween and to leave some posts standing, this leading to variation in the effect of reducing the capacitance.
In the manufacturing method of the past, the void it was not possible to perform good control the formation of the void height from a position that is above the upper surface of a wiring to a position that is below the lower surface of a wiring, so that unintended capacitance between the top and bottom of the void resulted in not being able to achieve a sufficient and accurate reduction in the capacitance.
In view of the above-described drawbacks in the prior art, an object of the present invention is to provide a semiconductor device which enables an arbitrary and highly accurate reduction the capacitance between adjacent wirings, thereby enabling the achievement of both a shrinking of the design rule and an increase in the speed of a semiconductor device, and to provide a method of manufacturing this semiconductor.
SUMMARY OF THE INVENTION
To achieve the above-noted object, in one aspect of the present invention, a semiconductor device according to the present invention is a semiconductor device comprising semiconductor elements formed on a surface of a substrate or a base insulation film, wirings connecting the elements and an interlayer insulation film, wherein the semiconductor device being provided with at least a longitudinal void portion at a position between adjacent two wirings through the interlayer insulation film, and further wherein one end of the void portion exceeding beyond a level corresponding to a top surface of the wirings, while the opposite end thereof exceeding below a level corresponding to a lower surface of the wirings.
And in a second aspect of the present invention, it is provided that a method of manufacturing a semiconductor device in which is formed elements and wirings, the method comprising steps of, forming an interlayer insulation film so as to cover all-over the wirings and areas between the wirings, using photoresist technology to perform simultaneously patterning operation so as to form a pattern for via hole apertures and to form a pattern for holes between the wirings, performing etching to form via holes using the photoresist as a mask, and simultaneously therewith, performing anisotropic etching to form apertures between the wirings, in the interlayer insulation film, selectively growing via hole burying metal only at the aperture that is to serve as a via hole, forming a second interlayer insulation film over the entire surface, so as to close off the top part only of the aperture in the area between wirings and of forming voids in the area between the wirings, and performing polishing and flattening the second interlayer insulation film until the via hole buried metal is exposed.
Further in a third aspect of the present invention it is also provided a method of manufacturing a semiconductor device in which is formed semiconductor elements and wirings, the method comprising steps of, forming an interlayer insulation film so as to cover over-all wirings and over areas between the wirings, using photoresist technology and dry etching technology to form apertures between the wirings, in the interlayer insulation film, forming a second interlayer insulation film over the entire surface of the first interlayer insulation film, so as to close off the top part only each one of the apertures, and forming a void in the areas between wirings, and performing polishing and flattening of the second interlayer insulation film so that the void is not exposed.
REFERENCES:
patent: 5512514 (1996-04-01), Lee
patent: 5792706 (1998-08-01), Michael et al.
patent: 5814558 (1998-09-01), Jeng et al.
patent: 6013575 (2000-01-01), Itoh
patent: 6107183 (2000-08-01), Sandhu et al.
patent: 62-5643 (1987-01-01), None
patent: 2-86146 (1990-03-01), None
patent: 2-240947 (1990-09-01), None
patent: 4-207055 (1992-07-01), None
patent: 5-21617 (1993-01-01), None
Dang Trung
Eaton Kurt
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