Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal
Patent
1985-01-25
1986-05-27
Saba, William G.
Metal treatment
Process of modifying or maintaining internal physical...
Chemical-heat removing or burning of metal
29576E, 29578, 29580, 148175, 148DIG26, 148DIG50, 148DIG103, 148DIG106, 156612, 156643, 156649, 156653, 156657, 357 34, 357 59, H01L 2120, H01L 21302
Patent
active
045913986
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
This invention relates to a method for manufacturing a semiconductor device, particularly an IC device of a bipolar transistor.
2. Background Art
As a prior art method for separating elements of a semiconductor integrated circuit (IC), there is known, for example, a selective oxidation (LOCOS) method. FIG. 1 is a cross-sectional view of a main part of a bipolar transistor IC that is manufactured by using the selective oxidation method. In the figure, reference numeral 1 designates a silicon semiconductor substrate of, for example, P type. Reference numeral 2 designates a collector embedded layer of N.sup.+ type, reference numeral 3 designates a collector region formed of an N type epitaxial growth layer, reference numeral 4 designates a base region, reference numeral 5 designates an emitter region, reference numeral 6 designates an SiO.sub.2 layer formed by the selective oxidation method and reference numeral 7 designates a portion from which a collector electrode is led out. Reference letters C, E and B respectively designate terminal for the collector, emitter and base. However, the selective oxidation process for manufacturing this bipolar transistor IC has the following problems. That is, if a bird's beak (the bird's beak protrudes to approximately 1.mu.) and a bird's head are generated as shown in FIG. 1, when the window is opened upon selective oxidation process and the window is opened for the emitter region, the mask alignments are respectively necessary; in this case, the tolerance including the alignment precision and the bird's beak is necessary; since the spacing between the base electrode leading-out portion and the emitter electrode leading-out portion is determined by the tolerance of the Al electrode, there is a limit to make the spacing narrow; the parasitic capacity of the collector is considerably affected by the region except the active region (so-called intrinsic portion); and the above problems give a limit on making the cell size smaller, etc.
While, in order to solve such problems, the present applicant has proposed a manufacturing method for producing a bipolar transistor IC as shown in FIG. 2 (refer to Japanese patent application No. 62701/1983). In this manufacturing method, an N.sup.+ type collector embedded layer 2 is formed first in a silicon semiconductive substrate 1 of, for example, P type. Thereafter, window apertures 9 and 10 are selectively formed through predetermined portions of the insulating film, for example, an SiO.sub.2 film 8 on the major surface of the substrate, namely, the portions corresponding to the active region and the collector electrode leading-out portion of the transistor. Then, the whole surface including the SiO.sub.2 film 8 and the window apertures 9 and 10 is subjected to the vapor phase growth treatment, whereby a single crystal silicon 16 is formed within the window apertures 9 and 10 and a polycrystalline silicon 17 is formed on the SiO.sub.2 layer 8. Thereafter, the single crystal silicon 16 and the polycrystalline silicon 17 are flattened and the polycrystalline silicon 17 is selectively removed. Then, formed on the single crystalline silicon 16 within the window aperture 9 are an N.sup.- type collector region 3, a P type base region 4 and an N.sup.+ type emitter region 5 and the polycrystalline silicon 17 is made as the base electrode lead-out portion, while formed on the single crystalline silicon 16 within the other window aperture 10 is an N.sup.+ type collector electrode lead-out portion, thus a bipolar transistor IC being formed. According to this manufacturing method, no bird's beak and no bird's head are produced, the parasitic capacity of the collector can be reduced and the cell size can be decreased, etc. However, as will be clear from FIG. 2, although the base region 4, the emitter region 5 and the emitter electrode lead-out portion 11 are formed in a self-alignment fashion, between the collector region 3 and the base region 4 there is a difference in size as L and l and they can not be formed in th
REFERENCES:
patent: 3611067 (1971-10-01), Oberlin et al.
patent: 4127931 (1978-12-01), Shiba
patent: 4168999 (1979-09-01), Vora et al.
patent: 4278987 (1981-07-01), Imaizumi et al.
patent: 4481706 (1984-11-01), Roche
patent: 4504332 (1985-03-01), Shinada
Anantha et al., "High-Voltage Power Transistor", I.B.M. Tech. Discl. Bull., vol. 16, No. 9, Feb. 1974, pp. 2874-2875.
Silvestri et al., "Reproducible Technique . . . Simultaneous Deposition . . . ", I.B.M. Tech. Discl. Bull., vol. 23, No. 2, Jul. 1980, pp. 819-820.
Asano Katsuaki
Kayanuma Akio
Ouchi Norikazu
Saba William G.
Sony Corporation
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