Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-10-20
1999-10-26
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438683, 438684, H01L 213205, H01L 214763
Patent
active
059727853
ABSTRACT:
Disclosed is a method for selectively forming silicon layers on diffusion layers of a MOS transistor so as to form an elevated structure in order to lower a resistance of the source/drain region. The method is aimed to lower the temperature required for the process of forming the elevated structure. In order to accomplish the foregoing object, the method of manufacturing a semiconductor device according to the invention is characterized in that titanium silicide layers are laminated in two steps. First, thin titanium films are grown on the diffusion layers and thereafter an annealing is applied to form titanium silicide layers; and then the titanium films remaining unreacted on the insulating films are removed. Thereafter, another silicon layer is selectively grown on the titanium silicide layers, followed by a new titanium layer. A second annealing step is performed to obtain a second titanium silicide layer laminated on the first titanium suicide layer. The titanium layers and the titanium silicide layers act as gettering films for oxygen from native oxide films formed on the surface.
REFERENCES:
patent: 4716131 (1987-12-01), Okazawa et al.
patent: 5798296 (1998-08-01), Fazan et al.
patent: 5863820 (1999-01-01), Huang
patent: 5874353 (1999-02-01), Lin et al.
Kitajima Hiroshi
Shishiguchi Seiichi
Booth Richard
NEC Corporation
Pompey Ron
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