Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-20
2002-12-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S301000, C438S305000, C438S303000, C438S680000, C438S682000, C438S683000, C438S592000, C257S388000, C257S412000, C257S382000, C257S383000
Reexamination Certificate
active
06489236
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a silicide layer and, more particularly, to a method for manufacturing a semiconductor device having a higher reliability and excellent short-channel characteristics.
(b) Description of the Related Art
For achieving a higher reliability of a semiconductor device, it is important to reduce the dimensions of the transistor elements. In particular, in a transistor element having a gate width on the order of 0.1 &mgr;m, a shallow junction structure with excellent short-channel characteristics is especially important. For example, the source-drain extension regions (referred to as SD-extensions hereinafter) needed for a reliable operation of the 0.1-&mgr;m-level transistor element should have a depth as low as 20 to 30 nm or below. To achieve such a shallow junction structure, several techniques are proposed and used heretofore which include an ion-implantation using low-energy ions, an ion-implantation for conversion from a polysilicon layer to an amorphous layer, and a short-time and low-temperature heat treatment for activation of impurity ions after the latter implantation. For example, in fabrication of the 0.1-&mgr;m-level transistor element, a heat treatment using a lamp annealer is conducted at a temperature of 1000° C. for 10 seconds after an ion-implantation for forming source/drain diffused regions.
A silicide process includes the steps of forming a refractory metal film on the surfaces of a polysilicon gate electrode and source/drain diffused regions having a specific conductivity-type and silicifying the refractory metal by reacting the same with underlying silicon in a heat treatment. The silicide process should meet the following requirements: that the silicide layer can be formed on a small-width gate electrode; and that the resistivity of the silicide layer does not depend on the heat treatment conducted at an ordinary temperature of 450° C. or a maximum temperature of 700° C. after formation of an overlying dielectric film. In the silicide process, a titanium silicide is generally used in a current 0.25 &mgr;m-rule MOSFET and a cobalt silicide is to be used in a next generation MOSFET having a smaller gate length for suppression of the line effect of the MOSFET. The term “line effect” as used herein means a phenomenon that a smaller gate length raises the sheet resistance of the silicide layer.
It is known that the silicon constituting the silicon substrate shifts or diffuses during the heat treatment at a temperature of 800° C. for 10 seconds in the silicide process. The shift of silicon atoms from the crystal lattice of the substrate generates an interstitial silicon atom and a vacancy in the silicon crystal lattice. These interstitial silicon atom and the vacancy significantly affect the rate of diffusion of implanted impurities such as boron and arsenic conducted for determining the electric characteristics of the transistors, and in particular, raises the diffusion rate of boron. More specifically, the silicide process uses a temperature lower than the temperature of a heat treatment for activation of diffused ions in the source/drain diffused regions, the silicide process has a larger influence upon the control of impurity diffusion compared to the heat treatment for activation.
A technique for solving the above problem is described in a literature “1999 Symposium VLSI Technology Digest of Technical Papers” pp49. This technique is described below, with reference to
FIGS. 1A
to
1
G showing consecutive steps of fabrication of an nMOSFET.
FIGS. 1A
to
1
G show a conventional fabrication process of an nMOSFET having a silicide layer. In
FIG. 1A
, the surface area of a semiconductor substrate
11
is doped with boron as p-type impurities to form a p-well
21
so that the p-well
21
defines specific electric characteristics such as threshold of the nMOSFET. A gate insulator film
13
is formed on the p-well
21
. The gate insulator film
13
is made of silicon oxide or silicon oxide nitride film including nitrogen at a concentration of 2 to 5%, in the case of a 0.1-&mgr;m-rule nMOSFET operating at a source voltage of 1.2 volts. A gate electrode
14
made of polysilicon having a thickness of 150 nm, for example, is formed on the gate insulator film
13
.
After forming the gate electrode
14
, as shown in
FIG. 1B
, a TiN film
45
is deposited on the entire surface by sputtering, followed by deposition of a silicon oxide film by using a CVD technique. The silicon oxide film is then subjected to etch-back thereof to leave a portion of the silicon oxide film on both the sides of the gate electrode
14
to form side-walls
55
, as shown in FIG.
1
C. Subsequently, as shown in
FIG. 1D
, an ion-implantation process is conducted to form source/drain diffused regions
17
, followed by a heat treatment for activation of the implanted ions. The top portion of the side-walls
55
is then etched by using hydrofluoric acid, followed by deposition of consecutive cobalt film
82
and TiN film
84
by sputtering, as shown on FIG.
1
E.
Subsequently, a heat treatment is conducted in a nitrogen ambient for silicidation, whereby a portion of the cobalt film formed on the source/drain diffused regions
17
is silicified to form cobalt silicide films
18
, as shown in
FIG. 1F
, At this stage, silicidation does not occur on the side surfaces of the polysilicon film constituting the gate electrode
14
and the substrate region in the vicinity of the source/drain regions
17
, whereby the cobalt silicide film is not formed thereon. Thereafter, remaining cobalt film not silicified and the TiN film on the sides of the gate electrode are removed by using sulfuric acid based etchant, as shown in FIG.
1
F.
In the state after the removal of cobalt and TiN, ion-implantation processes for forming SD-extensions
61
and for forming a pocket regions
62
which assures the short-channel characteristics of the MOSFET are conducted, followed by a heat treatment using a rapid thermal annealing technique, as shown in FIG.
1
G. Thereafter, known processes are conducted for forming contact-holes and interconnect layers similarly to a conventional fabrication process of the nMOSFET.
In the conventional silicide process, the shallow SD-extensions have a depth larger than a desired depth irrespective of the energy for the implanted ions being lowered as desired, because the implanted ions are thermally diffused to a larger depth region during the heat treatment for the silicidation. The depth of the junction formed by the thermal diffusion is far larger than the initial depth of the junction formed by the ion-implantation, the larger depth causing degradation of the short-channel characteristics of the MOSFET. Thus, a process is desired which is less susceptible to the heat treatment for silicidation with respect to the design depth for the shallow junction.
The literature as described above recites a process, wherein the silicide layer is formed before ion-implantation for forming the SD-extensions, thereby solving the above problem. However, the recited process raises another problem wherein the gate oxide film having a small thickness is damaged by the heat treatment for silicidation, thereby significantly lowering the reliability of the MOSFET. In addition, the temperature of a heat treatment conducted after a later ion-implantation step is not specified in the literature, whereby the recited process achieves only a limited advantage.
SUMMARY OF THE INVENTION
In view of the above problems in the silicide process in a conventional fabrication method for a MOSFET, it is an object of the present invention to provide a method for fabricating a semiconductor device including a MOSFET having excellent short-channel characteristics without degrading the reliability of the MOSFET.
The present invention provides a method for manufacturing a MOSFET including the steps of forming a gate electrode having a top surface including silicon and source/drain diffused
Imai Kiyotaka
Ono Atsuki
Everhart Caridad
Keshavan B
NEC Corporation
Young & Thompson
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