Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-12-11
2003-10-28
Karlsen, Ernest (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000
Reexamination Certificate
active
06638799
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device that employs an SOI (Silicon On Insulator) substrate, more particularly, to a method for manufacturing a semiconductor device that enhances the capability of an SOI device in fixing the electrical potential of an SOI layer more securely.
In recent years, a semiconductor device in which such elements as transistors are integrated and is used within electronic equipment has been strongly demanded to operate in higher speed and lower power consumption. In order to meet such strong demand, advanced technologies have been developed and the refinement and the reduction in parasitic capacitance of a semiconductor device have been thereby considered effective.
Note that the refinement of a semiconductor device means mainly the reduction in gate length of a MOS transistor. However, the shorter the gate length is, the further enhanced the short channel effect of a MOS transistor is. To prevent the enhancement of short channel effect, the following technology for forming the so-called pocket region has been conceived. That is, impurity ions of the conductivity type opposite to that of the conductivity type of a source/drain region are implanted into the regions located inside the source/drain regions at a tilt angle of 45 degrees with respect to a direction perpendicular to the principal surface of a semiconductor substrate.
In addition, as one of measures to reduce the parasitic capacitance of a semiconductor device, an SOI device has been conceived so that a semiconductor layer is formed on an insulating substrate and then a semiconductor device such as a transistor is formed in the semiconductor layer. However, there also has been found many difficult problems that were not solved by the conventional technology being fostered in the semiconductor device development employing a bulk semiconductor substrate.
A conventional SOI device consisting of CMOS transistor with a pocket region will be described below.
FIG. 7
is a cross sectional view of a conventional SOI device taken along a line in a channel direction (gate length direction).
As shown in
FIG. 7
, the CMOS type conventional SOI device comprises a silicon substrate
103
, a BOX (Buried Oxide) layer
104
formed in a region having a certain depth below the principal surface of the silicon substrate
103
,an oxide film
106
for element isolation formed as an STI (Shallow Trench Isolation) to separate a semiconductor layer
105
located on the BOX layer
104
into an n-type MISFET formation region denoted by Rnt and a p-type MISFET formation region denoted by Rpt, a gate insulating film
107
of a silicon oxide film formed on the semiconductor layer
105
, a gate electrode
108
formed on the gate insulating film
107
, a silicide layer
108
a
formed in the upper portions of the gate electrode
108
, and sidewalls
110
of a silicon oxide film formed on the side surfaces of the gate electrode
108
.
Furthermore, an n-type MISFET comprises, within the semiconductor layer
105
, n-type source/drain regions
111
formed in both regions beside the gate electrode
108
, silicide layers
111
a
formed in the upper portions of the n-type source/drain regions
111
, n-type LDD regions
113
formed inside the n-type source/drain regions
111
, p-type pocket regions
112
formed under the n-type LDD regions
113
and located inside the n-type source/drain regions
111
, a channel control region
114
including p-type impurities and formed just below the gate insulating film
107
, being interposed between the n-type LDD regions
113
, and a p-type well region
115
formed under the channel control region
114
so as to extend downward therefrom.
A p-type MISFET comprises, within the semiconductor layer
105
, p-type source/drain regions
119
formed in both regions beside the gate electrode
108
, silicide layers
119
a
formed in the upper portions of the p-type source/drain regions
119
, p-type LDD regions
121
formed inside the p-type source/drain regions
119
, n-type pocket regions
120
formed under the p-type LDD regions
121
and located inside the p-type source/drain regions
119
, a channel control region
122
including n-type impurities and formed just below the gate insulating film
107
, being interposed between the p-type LDD regions
121
, and an n-type well region
123
formed under the channel control region
122
so as to extend downward therefrom.
It should be noted that in the n-type MISFET formation region, Rnt, as the p-type pocket region
112
is formed under the n-type LDD region
113
doped with impurities at a low concentration, the pocket region suppresses the spread of the depletion layer of the LDD region
113
in the p-type well region
115
, whereby the short channel effect generated in the n-type MISFET is suppressed.
In the same manner as in the n-type MISFET, in the p-type MISFET formation region, Rpt, as the n-type pocket region
120
is formed under the p-type LDD region
121
doped with impurities at a low concentration, the pocket region suppresses the spread of the depletion layer of the LDD region
121
in the n-type well region
123
, whereby the short channel effect generated in the p-type MISFET is suppressed.
However, in the SOI device as above, each of the MISFET formation regions is isolated from each other by the BOX layer
104
and the oxide film
106
for element isolation formed as an STI. Owing to the specific structure of the SOI device described above, the electrical potential of the body regions right under the channel control region
114
of the n-type MISFET and that of the body regions right under the channel control region
122
of the p-type MISFET cannot be fixed via respective well regions
115
and
123
, whereas the electrical potential of a body region in a bulk silicon device employing a bulk silicon substrate is fixed. To prevent such phenomenon, in general, a body contact region shown in the following explanation is formed to fix the electrical potential of a body region.
FIG. 8A
is a plan view of a CMISFET that consists of the n-type MISFET and the p-type MISFET shown in
FIG. 7
, and simultaneously constitutes an inverter circuit.
FIG. 8B
is a cross sectional view of the CMISFET taken along a line orthogonal to a channel direction. However, note that in
FIG. 8A
sidewalls
110
are omitted for simplicity of illustration.
As shown in
FIGS. 8A and 8B
, a p-type body contact region
131
doped with p-type impurities at a high concentration and a silicide film
131
a
are formed in the n-type MISFET formation region, Rnt. This p-type body contact region
131
is formed to fix the electrical potential of the p-type well region
115
right under the channel control region
114
of the n-type MISFET and reduce substantially the resistance of the p-type well region. In addition, in the same manner as in the n-type MISFET, an n-type body contact region
141
doped with n-type impurities at a high concentration and a silicide film
141
a
are formed in the p-type MISFET formation region, Rpt. This n-type body contact region
141
is formed to fix the electrical potential of the n-type well region
123
right under the channel control region
122
of the p-type MISFET and reduce substantially the resistance of the n-type well region.
Furthermore, plugs
129
penetrating an interlayer insulating film
128
are formed therein reaching the surfaces of the gate electrode
108
, the source/drain regions
111
,
119
and the body contact regions
131
,
141
, whereby each of the above-stated portions are supplied with a voltage via the plugs
129
. In more detail, the body contact regions
131
and
141
are connected to the well regions
115
and
123
respectively via the corresponding pathway portions, and thus by supplying a voltage to the plugs
129
that reach the surfaces of the body contact regions
131
and
141
, the inverter circuit is configured to fix the electrical potential of the well regions
115
and
123
just below the channel control regions
114
Hollington Jermele
Karlsen Ernest
Nixon & Peabody LLP
Studebaker Donald R.
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