Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2002-04-22
2003-09-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S637000, C257S758000, C257S750000
Reexamination Certificate
active
06614096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and also to a semiconductor device. In particular, this invention is related to a semiconductor device comprising a multi-layer wiring of damascene wiring structure wherein a low dielectric constant insulating film is employed as an interlayer material. This invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
As the density of ULSIs has been increasingly enhanced in recent years, the problem of retardation in propagation of wiring is now increasingly serious. It is known, as a method for solving this problem, to lower the dielectric constant of interlayer insulating film or to minimize the electric resistance of wiring material. The lowering of dielectric constant of interlayer insulating film can be realized by using an interlayer insulating film material having a low dielectric constant, i.e. as low as not more than 3.0 in relative dielectric constant. For example, the use of polysiloxane film is effective in this respect. As for minimizing the electric resistance of wiring material, the use of copper wiring is well known.
Even though the use of copper wiring is advantageous in minimizing the electric resistance of wiring, it is very difficult to perform the fine working on copper wiring, so that a damascene process is generally employed for forming a multi-layer wiring structure by using copper wiring. According to the damascene process, an interlayer insulating film is formed at first, and then, a groove having the same width as that of the wiring desired to be obtained is formed. Thereafter, the groove is filled with a wiring material, and then, any redundant metal is removed from the surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method to form a multi-layer wiring structure.
In a case where polysiloxane such as methylpolysiloxane is employed as an interlayer insulating film, a silicon oxide film
16
may be laminated on a methylpolysiloxane film
15
by a CVD (Chemical Vapor Deposition) process as shown in
FIG. 1A
in order to enhance the dry etching (plasma) resistance or the CMP resistance thereof. As shown in
FIG. 1A
, the methylpolysiloxane film
15
is formed over the surface of a semiconductor substrate
12
, on which an insulating film
10
, an additional insulating film
9
where a lower layer wiring
11
is buried therein through a barrier metal layer
8
, and a silicon nitride film
14
have been successively deposited in advance. The interlayer insulating film constituted by this laminate structure is provided, as shown in
FIG. 1B
, with an upper wiring
19
which has been formed by a process wherein a contact hole
13
and a wiring groove
17
are formed in the interlayer insulating film, and then, a barrier metal
18
and a metal constituting a wiring material are buried in these hole and groove, which is followed by a CMP treatment to form the upper wiring
19
. However, there is a high possibility that the silicon oxide film
16
formed by the CVD method is peeled away (as indicated by
20
) during the processes such as the CMP working and heat treatments, thereby degrading the reliability of the semiconductor device.
As described above, it is now desired, in the manufacture of a semiconductor device which is capable of lowering the dielectric constant of the interlayer insulating film and of minimizing the electric resistance of wiring material, to take some measures to prevent the interlayer insulating film from being peeled away.
BRIEF SUMMARY OF THE INVENTION
A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises:
forming a first insulating film above a semiconductor substrate, the first insulating film being made of a low dielectric constant material and containing carbon;
subjecting the first insulating film to a surface treatment to reduce the carbon concentration of a surface layer of the first insulating film, thus turning the surface layer into a low carbon concentration layer;
forming a second insulating film on the low carbon concentration layer;
forming a groove in the first and second insulating films for burying a metal therein;
burying the metal in the groove formed in the first and second insulating films; and
polishing a surface of the metal buried in the groove to form a metal wiring.
A semiconductor device according to another embodiment of the present invention comprises:
a semiconductor substrate;
an interlayer insulating film formed above the semiconductor substrate, the interlayer insulating film containing a first insulating film comprising carbon and made of a low dielectric constant material and a second insulating film formed on the first insulating film; and
a damascene wiring structure formed in the interlayer insulating film;
wherein the first insulating film is provided, on one surface thereof facing the second insulating film, with a low carbon concentration layer where the concentration of carbon is minimized.
REFERENCES:
patent: 6303523 (2001-10-01), Cheung et al.
patent: 6333255 (2001-12-01), Sekiguchi
patent: 6348725 (2002-02-01), Cheung et al.
Kojima Akihiro
Miyajima Hideshi
Clark Sheila V.
Kabushiki Kaisha Toshiba
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