Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2003-06-25
2004-10-12
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S238000, C438S381000
Reexamination Certificate
active
06803292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device having an overlay mark. More particularly, the present invention relates to a method for manufacturing a semiconductor device wherein mismatching between a region in which the semiconductor device is formed and an overlay mark may be minimized by forming the overlay mark to have a pattern identical to that of the region, and a semiconductor device having the overlay mark.
2. Description of the Related Art
In general, an electric circuit of a semiconductor device is manufactured through repeating a series of unit processes such as deposition, photolithography, etc., in order to form circuit patterns on a substrate. In a photolithography process, a photoresist film is exposed using a mask in which a circuit pattern is formed. The photoresist film is developed after being coated on a wafer, thereby transferring the circuit pattern of the mask onto a photoresist pattern on the wafer. Then, a film under the photoresist pattern is etched using the transferred photoresist pattern as an etching mask so that the circuit pattern is formed in the film.
When film patterns are formed by repeatedly performing the photolithography process, alignment between an upper pattern and a lower pattern becomes critical.
Alignment is generally performed by reticle alignment and wafer alignment in an exposure apparatus during the photolithography process. Adjustment of the alignment is performed using correction data obtained by an overlay inspection for a photoresist pattern after exposure and development steps.
In the overlay inspection, vertical and horizontal misalignment, rotation, and orthogonality are measured between an overlay mark formed on the lower pattern (a main scale) and an overlay mark formed on the upper pattern (a vernier), thereby generating correction data to apply in a subsequent exposure step.
The overlay mark, generally having a box shape, is formed on a die cutting line of a wafer (a scribe line).
However, the conventional overlay mark may not be useful for an overlay inspection of a real pattern because the conventional overlay mark has dimensions and shape different from those of the real pattern in a region where a semiconductor device is formed.
The prior art discloses a method for measuring energy applied in an exposure step and for determining a focusing value by comparing standard values with measured values in a photolithography process. The measured values include length variations in a line and space of a cell matching adopter when the length variations are measured with an overlay apparatus after the exposure step is performed. The cell matching adopter has a line and space identical to those of a real pattern, and is included in a monitoring mark formed on a scribe line of a wafer during formation of a mask.
However, the cell matching adopter may not be useful for an inspection of the real pattern because the cell matching adopter is formed around a vernier only, and is identical to the real pattern in size, but not shape.
SUMMARY OF THE INVENTION
Therefore, in an effort to solve the problems mentioned above, it is a feature of an embodiment of the present invention to provide a method for manufacturing a semiconductor device capable of measuring an overlay condition of a real pattern by forming a first mark of an overlay mark identical to a first pattern of the real pattern and by forming a second mark of the overlay mark identical to a second pattern of the real pattern.
It is another feature of an embodiment of the present invention to provide a semiconductor device for measuring an overlay condition of a real pattern with an overlay mark including a first mark identical to a first pattern of the real pattern and a second mark identical to a second pattern of the real pattern.
To provide a feature of an embodiment of the present invention, there is provided a method for forming a semiconductor device including forming a first pattern for a semiconductor device in a semiconductor device formation region of a semiconductor substrate and simultaneously forming the first pattern in a first mark formation region of the semiconductor substrate; forming a second pattern for the semiconductor device on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously forming the second pattern in a second mark formation region of the semiconductor substrate; and inspecting the first pattern in the first mark formation region and the second pattern in the second mark formation region for misalignments.
In this case, the first mark formation region may be a box shaped main scale formation region, and the second mark formation region may be a box shaped vernier formation region. Also, the first pattern may be an active pattern in a DRAM cell region, and the second pattern may be a word line pattern in the DRAM cell region.
In accordance with a feature of an embodiment of the present invention, for optical proximity correction (OPC), a scattering bar may be formed at an edge of a pattern in a mask corresponding to the first pattern in the first mark formation region, and another scattering bar may be formed at an edge of a pattern in a mask corresponding to the second pattern in the second mark formation region.
To provide another feature of an embodiment of the present invention, there is provided a semiconductor device having an overlay mark, the overlay mark including a first mark formed in a first mark formation region of a semiconductor substrate and a first pattern formed in a semiconductor device formation region of the semiconductor substrate, wherein the first mark and the first pattern are formed simultaneously by a same process such that the first mark has a shape identical to a shape of the first pattern, and a second mark formed in a second mark formation region of the semiconductor substrate and a second pattern formed in the semiconductor device formation region of the semiconductor substrate, wherein the second mark and the second pattern are formed simultaneously by a same process such that the second mark has a shape identical to a shape of the second pattern.
The first pattern may be an active pattern in a DRAM cell region, and the second pattern may be a word line pattern in the DRAM cell region
REFERENCES:
patent: 5308682 (1994-05-01), Morikawa
patent: 5311061 (1994-05-01), Sheck
patent: 5580812 (1996-12-01), Ikemasu et al.
Kim Dae-Joung
Oh Seok-Hwan
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Tsai H. Jey
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