Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-30
2002-09-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S686000, C438S687000
Reexamination Certificate
active
06451688
ABSTRACT:
This application is based upon and claims priority of Japanese Patent Application No. 2000-369323, fled, the contents being incorporated herein by reference.
FIELD OF THE PRESENT INVENTION
The present invention concerns an improved method for forming an opening which possesses a step differential patternwise.
BACKGROUND OF THE INVENTION
Prospects of practically mass-producing Cu (copper) wire layers in place of extant Al (aluminum) wire layers have come to be vigorously investigated from the standpoint of lowering the intrinsic electrical resistance values of wire layers, which has been become urgent in response to the size reductions of wire layers, which inevitably accompany attempts to reduce the sizes of semiconductor devices. Unlike the Al (aluminum), however, the Cu (copper) is an extremely difficult material to process due to production process-related limitations, and it is indispensable to develop unprecedented techniques for both blanketwise formation processes and patterning processes, and accordingly, a so-called “dual damascene structure,” which possesses a downwardly protruding cross-sectional shape, has come to be proposed as the shape of an opening for configuring a wire layer within an interlayer insulating film.
The present invention provides a technique which is most desirable as an improved opening formation process for this dual damascene structure.
First, dual damascene wiring processes of the prior art will be explained with reference sequentially to
FIGS. 1 through 6
.
FIGS. 1 through 6
show cross-sectional views during the respective processes of the dual damascene wiring technique of the prior all, and cross-sectional appearances of the apparatus corresponding to the respective processes are thereby shown modelwise. The cross-sectional structure of the dual damascene wire layer is characterized by an approximately downward protrusion, and this technique of the prior art may therefore be said to be founded roughly on the following concept. In other words, an interlayer insulating film is first etched halfway by using a resist mask which possesses a large opening, and after it has subsequently been substituted with a resist mask which possesses a smaller opening, a window is formed on the interlayer insulating film in such a way that the segment of the interlayer insulating film the thickness of which has become reduced as a result of the halfway etching alone will become etched through to the lower wire layer.
Next, such a technique of the prior art will be explained in detail below, see FIG.
1
.
As far as the dual damascene wiring processes of the prior art are concerned, the impurity electroconductive layer (
2
), which serves as a wire layer, is first configured within the semiconductor substrate (
1
), and subsequently, the etching stopper (
3
), the interlayer insulating film (
4
), and the resist mask (
5
) are formed in proper order above it. The resist mask (
5
) is patterned by using a well-known photolithographic technique. Next, the interlayer insulating film (
4
) is selectively removed based on a dry etching technique via the window which has been formed within the resist mask (
5
) photolithographically, as shown in FIG.
2
.
In such a case, the etching of the interlayer insulating film (
4
) is stopped at a stage where the etching depth remains shallow enough not to reach the base underneath completely, as a result of which a depression is configured within the interlayer insulating film (
4
). The resist mask (
5
) is subsequently removed by means of ashing, as shown in FIG.
3
.
The resist mask (
6
) is coated anew on the entire plane of the interlayer insulating film (
4
), including the depression configured earlier. A window is formed on this resist mask (
6
) based on a well-known photolithographic technique. As
FIG. 4
illustrates, the width of the window thus formed is sufficiently narrower than the width of the depression while the step differential imputed to the depression is being bared to its bottom.
Next, the interlayer insulating film (
4
) is selectively etched by using the resist mask (
6
). In such a case, the etched segment of the interlayer insulating film (
4
) includes the step differential, and therefore, in a case where the etching is terminated at the stage where the etching stopper (
3
) has become bared to the bottom of the interlayer insulating film (
4
), the step differential shown in
FIG. 5
, which has fundamentally inherited the traits of the initial step differential, comes to emerge within the window. Subsequently, the resist mask (
6
) is removed by means of ashing, as shown in FIG.
5
.
Next, the etching conditions are redesignated, and the etching stopper (
3
), which has come to become bared to the bottom of the interlayer insulating film (
4
), is removed, as a result of which the window becomes etched through to the impurity electroconductive layer (
2
). Thus a dual damascene window with a downwardly protruding shape is formed in the interlayer insulating film (
4
), as shown in FIG.
6
.
A thin tantalum nitride (TaN) layer (not shown), furthermore, is formed on the inner wall of the dual damascene window by means of sputtering. This layer, which serves as a barrier layer for preventing the diffusion of a copper (Cu) wire layer to be formed later toward the interlayer insulating film (
4
), is an indispensable element for the copper (Cu) wire constitution of a dual damascene structure. Next, a thin copper (Cu) seed layer (not shown) is formed on the surface of the tantalum nitride (TaN) layer by means of sputtering. This copper (Cu) seed layer serves the function of a seed layer during a plating process whereby the interior of the dual damascene window is completely filled with the copper (Cu) layer (
9
). A film that constitutes the copper (Cu) layer (
9
) is formed at a sufficient thickness based on the plating method in such a way that it will bulge from the window initially, but the bulge beyond the dual damascene window is subsequently removed based on the CMP (chemicomechanical polish) method, as a result of which the cross-sectional shape shown in
FIG. 6
is achieved.
Thus, the processes of the prior art for forming a copper (Cu) dual damascene wire constitution has been explained.
The dual damascene wiring technique of the prior art is plagued with fatal problems which cannot be overlooked in the context of size reduction, and they will be explained below.
FIG. 7
, which corresponds to the process shown in
FIG. 3
, which has been referred to earlier, is a diagram which shows a cross-sectional view of a state where the process is in progress and which points out the first problem of the prior art. The etching stopper (
3
) and the interlayer insulating film (
4
) are formed in proper order above the semiconductor substrate (
1
), on the surface of which has been formed the impurity electroconductive layer (
2
) previously, and a depression is formed patternwise within the interlayer insulating film (
4
) by means of selective etching. In such a case, the interlayer insulating film (
4
) is not etched through as a result of etching, but rather, the etching is terminated halfway along the thickness of the interlayer insulating film (
4
) in the context of configuring said depression. Next, the resist mask (
6
) is formed blanketwise over the entire plane of the interlayer insulating film (
4
), including the depression, and a subsequent operation for patterning a resist mask opening is carried out based on a well-known photolithographic method. In a case where a resist of the negative type is hereby assumed to be used, exposure beams become scattered under the pervasion of the step differential in the interlayer insulating film (
4
), and accordingly, patterning irregularities are incurred in the region on which the resist mask opening is to be formed during an operation for transferring a negative pattern. A mask is configured on a plane that includes the step differential in the case of the transfer of the negative pattern, and the step differential segment should ideally remain une
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Gurley Lynne
Niebling John F.
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