Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-28
2001-12-04
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S648000, C438S687000, C438S692000
Reexamination Certificate
active
06326299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, more particularly to a method for forming metallic wirings of a semiconductor device through polishing and a semiconductor device manufactured using the method.
2. Description of the Related Art
In recent years, planarization of the surfaces of wiring boards has been increasingly valued for large scale semiconductor integrated circuits (LSIs). One of the representative techniques for such the planarization is the Chemical Mechanical Polishing (CMP: hereafter, to be described as polishing otherwise specially defined), which is disclosed in, for example, the U.S. Pat. No. 4944836. According to this method, for example, a metal film for wiring is formed on a silicon substrate (wiring board) on which an LSI is to be formed, then the metal film is treated through well-known lithography and Reactive Ion Etching (RIE) techniques, thereby forming the object wiring pattern. After that, an insulating layer is formed on the wiring pattern. If the surface of the insulating layer is planarized through polishing, the fabrication accuracy of the wiring to be formed in the upper layer will be improved more effectively.
On the other hand, the damascene method that forms metallic wirings through polishing steps is also a focus of attention. According to the damascene method, an insulating film is formed on a wiring board at first, then grooves are formed in the insulating film for the wiring using both well-known lithography and RIE techniques. On the board with those grooves is then deposited a metal film for wiring. After that, the metal film except for the portion inlaid in each groove is removed through polishing, so that inlaid metal lines are formed there. This technique is disclosed in, for example, Japanese Patent Laid-Open No.2-278822. This method, which is effective especially when lines are to be formed with a copper based alloy whose fine fabrication by RIE is difficult, is also now under study as a method for fine fabrication of aluminum wiring patterns.
The details of the conventional damascene method are introduced in the official gazette of Japanese Patent Laid-Open No.10-214834 and in the publication of Proceedings CMP-MIC Conference (pp.415-422). Those examples describe a layered film consisting of tungsten and titanium respectively. Hereunder, the damascene method will be described on the basis of those examples with reference to FIG.
3
. At first, an insulating layer
31
is formed on a wiring board
30
as shown in FIG.
3
(
a
). Then, in the insulating layer
31
are formed depressions such as grooves or holes (to be referred to as grooves
32
generically) to be used as wirings and interlevel portions. After that, a lower metallic layer
32
and an upper metallic layer
33
are formed in order so as to cover the insulating layer
31
. The lower metallic layer
32
consists of titanium and the lower metallic layer
33
consists of tungsten.
After that, both upper and lower metallic layers
32
and
33
except for the grooves are removed through polishing as shown in FIG.
3
(
b
). Since the upper metallic layer
33
to be polished in the dense area of each groove pattern is substantially thinner than that of other areas provided with no pattern, the polishing of the upper metallic layer
33
is ended earlier in the pattern dense area than in other non-pattern areas. Therefore, when the lower metallic layer
32
and the first insulating layer
31
are exposed, part
33
a
of the upper metallic layer
33
still remains unfinished in each no-pattern area. And, if the polishing is continued until the lower metallic layer
32
is removed completely, phenomena referred to as erosion and dishing occur. The erosion means a phenomenon that the surface of the insulating layer
31
is depressed by a depth E
1
more in each pattern dense area than in other non-pattern areas as shown in FIG.(
c
). The dishing means a phenomenon that the surface of the upper metallic layer
33
is depressed by a depth D
1
more in each groove from the surface of the surrounding insulating layer
31
. It is also reported that a localized erosion occurs at a depth of LE especially at each boundary between a pattern dense area and a no-pattern area. It is also reported that this localized erosion depends on the relative moving directions of both polishing platen and wiring board, as well as the type of the polishing pad, etc.
The reason why such a height difference occurs is explained as follows. Generally, a polishing agent for the layered metals causes the polishing rate to be reduced in order of upper metallic layer, lower metallic layer, and insulating layer. In particular, a significant difference appears between polishing rates for the lower metallic layer and the insulating layer. In most cases, the polishing rate of the insulating layer is only a factor of scores with respect to the polishing rate for the lower metallic layer. Since the polishing rates for the upper and lower metallic layers
32
and
33
are larger than that of the insulating layer such way, the surfaces of the upper and lower metallic layers
32
and
33
in each pattern dense area are depressed deeply from the surface for the insulating layer
31
when the polishing ends. Consequently, a large polishing force is concentrated effectively at each projection of the insulating layer
31
.
The polishing of the insulating layer is thus accelerated in each pattern dense area according to this difference between such the polishing forces, thereby causing a large height difference. And, a total of such an erosion depth E
1
, a localized erosion depth LE, and a dishing depth D
1
would often reach ½ of the initial depth of the groove. If an inlaid metal is used for wiring, therefore, such a depth will increase the resistance of the object wiring significantly. In addition, if an attempt is made to form a multi-layered wiring on this layer using the damascene method, the height differences generated by such the erosion depth E
1
, the localized erosion depth LE, and the dishing depth D
1
will affect the wiring in the upper layer, causing the metallic layer to be left unpolished in each depression. And, this unpolished portion of the metallic layer causes short-circuits of the wiring in the upper layer.
There is a two-step polishing method proposed for minimizing the difference between polishing rates effectively by eliminating height differences as described above. Concretely, the polishing is finished once after the polishing of the upper metallic layer
33
is almost finished as shown in FIG.
3
(
d
). Since the polishing rate for tungsten is five times faster than that for titanium, the polishing can be finished before the titanium film is removed completely. Next, the polishing agent is changed to another that contains silica abrasive powder and potassium hydroxide or ammonium hydroxide, thereby polishing the titanium of the lower metallic layer
32
. The use of this polishing agent can almost equalize the polishing rate between the insulating film
31
and titanium. The polishing method will thus reduce the erosion depth E
2
and the dishing depth D
2
as shown in FIG.
3
(
d
), thereby improving the planarization of the surface of the layer. This conventional two-step polishing method aims at elimination of polishing non-uniformity caused by the polishing of an upper or middle layer (titanium containing nitrogen, if necessary) by stopping the polishing (the first polishing) on the surface of the titanium film, which is a lower metallic layer. The first polishing is donefor layers including a thick tungsten film, which is an upper metallic layer, as well as a middle titanium nitride layer. The conventional two-step polishing method further aims at actual reduction of the non-uniformity of polishing only in the second polishing of the lower metallic layer. In the second polishing, the polishing rates for both lower metallic layer and insulating layer should preferably be equal
Hom-ma Yoshio
Imai Toshinori
Kondo Seiichi
Ohashi Naofumi
Owada Nobuo
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Quach T. N.
LandOfFree
Method for manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2562696