Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2006-07-04
2006-07-04
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S697000, C438S700000
Reexamination Certificate
active
07071107
ABSTRACT:
There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.
REFERENCES:
patent: 6191002 (2001-02-01), Koyanagi
patent: 6489252 (2002-12-01), Goo et al.
patent: 2004/0043581 (2004-03-01), Lin et al.
patent: 354441 (2002-09-01), None
Heo et al., “Void Free and Low Stress Shallow Trench Isolation Technology Using P-SOG For Sub 0.1 μm Device”, 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 132-133, 2002.
Notification for Filing Opinion mailed Nov. 8, 2005, issued by the Korean Patent Office in counterpart Korean Application No. 10-2003-68155 and English translation thereof.
Hieda Katsuhiko
Kawasaki Atsuko
Kiyotoshi Masahiro
Tachibana Katsuhiko
Yamazaki Soichi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Norton Nadine
Tran Binh X.
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