Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-15
2003-11-04
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S460000
Reexamination Certificate
active
06642137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a package structure and method for integrated circuits, and in particular, to a package structure in which integrated circuits can be easily adhered to the substrate in order to solve the problem caused by the overflowed glue, thereby implementing a chip scale package.
2. Description of the Related Art
In the current technological field, every product needs to be light, thin, and small. Therefore, it is preferable that the integrated circuit has a small volume in order to meet the demands of the products. The technology of a chip scale package can reduce the volume of an integrated circuit after packaging, thereby making the product small, thin, and light.
Referring to
FIG. 1
, in the technology of a conventional package or a chip scale package, when the integrated circuit
10
is adhered onto the substrate
12
, the glue often overflows into the substrate
12
from the adhering surface of the integrated circuit
10
due to the improper control of the adhesive layer
14
. Thus, the overflowed glue
16
may cover the signal input terminals
18
of the substrate
12
and influence the wire bonding processes in which a plurality of wirings
20
are formed. As a result, in order to prevent the signal input terminals
18
of the substrate
12
from being covered by the overflowed glue
16
, the substrate
12
has to be enlarged. By doing so, the signal input terminals
18
are far away from the integrated circuit
10
. In this case, the signal input terminals
18
of the substrate
12
are free from being covered by the overflowed glue
16
. Therefore, the problem caused by the overflowed glue can be solved.
However, the overall volume of the package of the integrated circuit enlarges as the size of the substrate
12
increases. Thus, a chip scale package cannot be implemented, and-the product cannot be made small, thin, and light.
To solve this problem caused by the overflowed glue, there is provided a package structure in which integrated circuits can be easily adhered to the substrate, thereby implementing a chip scale package.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a package structure and method for the integrated circuit for solving the problem caused by the overflowed glue and for facilitating the manufacturing processes.
It is therefore another object of the invention to provide a package structure and method for the integrated circuit capable of scaling down the package structure to make the products small, thin, and light.
According to one aspect of the invention, a package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connected to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits.
According to another aspect of the invention, a method for manufacturing a package structure of integrated circuits includes the steps of: providing a substrate; providing a wafer formed with a plurality of integrated circuits, a plurality of scribing lines being formed between adjacent integrated circuits; scribing the wafer along each of the scribing lines to predetermined depths using a scribing tool having a larger width so as to form recesses at two sides of each of the integrated circuits; cutting the wafer along each of the scribing lines using a scribing tool having a smaller width to separate each of the integrated circuits; coating an adhesive layer to adhere the integrated circuit onto the substrate; electrically connecting the plurality of wirings to the integrated circuit and to the substrate; and providing a glue layer for sealing the plurality of wirings and the integrated circuit.
According to the structure and method of the invention, the problem caused by the overflowed glue in the integrated circuit can be effectively avoided.
REFERENCES:
patent: 5736453 (1998-04-01), Kadonishi
patent: 5742100 (1998-04-01), Schroeder et al.
patent: 6198165 (2001-03-01), Yamaji et al.
patent: 6207473 (2001-03-01), Hirai et al.
patent: 6307479 (2001-10-01), Wang
Peng Chen Pin
Wu Ji-chen
Yeh Nai Hua
Dang Phuc T.
Kingpak Technology Inc.
Pro-Techtor Inter-national Services
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