Method for manufacturing a narrowed sidewall spacer in a periphe

Details Method for manufacturing a narrowed sidewall spacer in a periphe Method for manufacturing a narrowed sidewall spacer in a periphe

1992-10-26

1994-03-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 437 60, 437919, H01L 2170, H01L 2700

Patent

active

052963993

ABSTRACT:
A method for manufacturing ULSI semiconductor memory devices is disclosed which uses an insulating film to form a side wall spacer of the gate electrodes of transistors formed in the peripheral circuit section of a memory device. This scheme prevents surface deterioration of the underlying structure during an etching process for manufacturing of a cell capacitor of a memory cell device cell array portion. The insulating film includes a laminated film composed of a thin oxide film and an etch blocking film formed on the oxide film. Due to the etch blocking film, the oxide film can be made thin, resulting in the formation of side wall spacers that are appropriately narrow. Thus, the function and operating speed of the peripheral circuit transistors is improved.

REFERENCES:
patent: 4426764 (1984-11-01), Kosa et al.
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 4984200 (1991-01-01), Saitoo et al.
patent: 5025295 (1991-06-01), Kuestars et al.
patent: 5028990 (1991-07-01), Kotaki et al.
patent: 5063431 (1991-11-01), Ushima

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