Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-12
2001-07-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S645000
Reexamination Certificate
active
06261941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to microfabrication techniques and, in particular, to a method for forming multiple layers of a wiring substrate and for interconnecting electrical connections on the multiple layers.
2. Related Art
Wiring substrates are typically used to electrically connect various components or devices of an electronic system. For example, a computer or other electrical system often utilizes various components including, but not limited to, many different types of passive elements and integrated circuits. These components are usually coupled to a wiring substrate that provides electrical connections between the components. For example, one type of wiring substrate used by many electrical systems is a printed wiring board, sometimes referred to as a “printed circuit board.” Printed wiring boards typically use an epoxy-glass laminate as a dielectric layer and include copper traces that electrically connect the components that are coupled to the printed wiring board. Most copper traces are narrow lines of copper that extend from an electrical contact of one component to an electrical contact of another component. The copper traces do not necessarily follow a straight line path from one component to another component but instead usually bend or curve to prevent the copper traces from shorting with each other.
Other major types of wiring substrates include ceramic and thin film substrates that enable a higher wiring density (i.e., length of wire per unit area) than conventional printed circuit boards. However, the cost of manufacturing the ceramic and thin film substrates is much greater than the cost of printed wiring boards. Therefore, the use of ceramic and/or thin film substrates has been limited.
To increase the capacity of wiring substrates (i.e., printed circuit boards, ceramic substrates, or thin film substrates), the number of layers of the wiring substrate is usually increased. Therefore, many conventional wiring substrates are multilayer structures. Furthermore, to provide vertical interlayer connectivity in multilayer wiring substrates, vias (in multilayer ceramic and multilayer thin film) and plated through holes (in multilayer printed wiring board) are formed.
A via is a vertical connection that electrically connects a conductive connection of one layer to a conductive connection of another layer. Unfortunately, existing techniques for via formation (i.e., filling and stacking) involve expensive and complex planarization processes, thereby increasing the cost and decreasing the yield of manufacturing wiring substrates. In fact, the high costs associated with conventional via filling and stacking prevent their use in many applications.
On the other hand, typical plated through holes are inexpensive and simple to fabricate but are relatively large compared to vias and pass through all of the layers of the wiring substrate. Therefore, a significant amount of space within the wiring substrate is taken up by plated through holes, resulting in a low wiring efficiency.
Consequently, conventional techniques for interconnecting layers of a multilayer substrate are expensive or inefficient. Thus, a heretofore unaddressed need exists in the industry for providing an inexpensive and efficient method of manufacturing a multilayer wiring substrate.
SUMMARY OF THE INVENTION
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed herein. The present invention can be viewed as providing a method for manufacturing a multilayer wiring substrate. Briefly described, the method can be broadly conceptualized by the following steps: forming a first conductive connection on a first insulating layer; forming a conductive post on the first conductive connection; forming a second insulating layer on the first conductive connection, the first insulating layer, and the conductive post; exposing the conductive post by removing a portion of the second insulating layer; and forming a second conductive connection on the second insulating layer such that the second conductive connection is electrically coupled to the first conductive connection via the conductive post.
In accordance with another feature of the present invention, the second insulating layer is formed via dry film lamination.
In accordance with another feature of the present invention, the conductive post is exposed via a surface roughening process.
In accordance with another feature of the present invention, a hole is formed in the second insulating layer to expose the conductive post. This hole allows the second conductive connection to be electrically coupled to the conductive post.
In accordance with another feature of the present invention, a press is applied to the surface of the second insulating layer in order to planarize the surface of the second inuslative layer.
The present invention has many advantages, a few of which are delineated hereafter, as mere examples.
An advantage of the present invention is that expensive planarization steps are not required in forming planar multilayer wiring substrates.
Another advantage of the present invention is that wiring substrates can be easily manufactured.
Another advantage of the present invention is that manufacturing costs of wiring substrates can be significantly reduced.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention, as is defined by the claims.
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Li Weipang
Tummala Rao R.
Chaudhuri Olik
Georgia Tech Research Corp.
Ha Nathan W.
Thomas Kayden Horstemeyer & Risley, L.L.P.
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