Method for manufacturing a membrane

Details Method for manufacturing a membrane Method for manufacturing a membrane

2000-07-13

2003-01-28

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S705000, C438S753000

Reexamination Certificate

active

06511913

ABSTRACT:

FIELD OF THE INVENTION
The present invention concerns a method for manufacturing a membrane.
BACKGROUND INFORMATION
It is believed that there are methods for producing a membrane in which an n-doped epitaxy layer is applied on a p-doped substrate. In a further step, a recess is then etched by starting the etching from the backside of the substrate and stopping at the p-n junction between the substrate layer and epitaxy layer. The recess introduced in this manner defines the geometric dimensions of the membrane.
SUMMARY OF THE INVENTION
The exemplary method of the present invention is believed to have the advantage that the thickness of the membrane can be reduced. In so doing, it is not necessary to reduce the thickness of the epitaxy layer.
Further advantages may result from the following features. The p-doping is introduced into the epitaxy layer particularly simply by the use of a mask and applying a dopant in the substrate. In so doing, the dopant can be introduced both from the vapor phase and by implantation. In addition, the mask allows a patterned application of the p-doping. When it extends over the entire area of the membrane, then the total thickness of the membrane can be reduced. Furthermore, it is also possible to form only partial areas, particularly edge areas, of the membrane so that they are thinner by introducing the p-doping. Individual areas of the membrane can also be formed thicker by introducing an n-doping. In this context, an embodiment may be particularly advantageous in which the mid-region of the membrane is thickened and the edge areas are formed to be thinner, since a stress (or voltage) concentration is thus effected in the edge areas. By the introduction of piezoresistors in the epitaxy layer and of integrated circuits, sensors can be produced which verify stress (or voltage) states in the membrane.


REFERENCES:
patent: 5068203 (1991-11-01), Logsdon et al.
patent: 5726066 (1998-03-01), Choi

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