Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-04-12
2010-10-05
Loke, Steven (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S760000, C257S640000
Reexamination Certificate
active
07807563
ABSTRACT:
In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
REFERENCES:
patent: 5067673 (1991-11-01), Fong
patent: 5260600 (1993-11-01), Harada
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5759913 (1998-06-01), Fulford et al.
patent: 5792706 (1998-08-01), Michael et al.
patent: 5837618 (1998-11-01), Avanzino et al.
patent: 6208015 (2001-03-01), Bandyopadhyay et al.
patent: 6211057 (2001-04-01), Lin et al.
patent: 6399476 (2002-06-01), Kim et al.
patent: 6423629 (2002-07-01), Ahn et al.
patent: 6440839 (2002-08-01), Partovi et al.
patent: 6445072 (2002-09-01), Subramanian et al.
patent: 6524948 (2003-02-01), Tamaoka et al.
patent: 6686643 (2004-02-01), Schwarzl et al.
patent: 6803318 (2004-10-01), Qiao et al.
patent: 6861332 (2005-03-01), Park et al.
patent: 6914011 (2005-07-01), Hayashide et al.
patent: 7033926 (2006-04-01), Schindler et al.
patent: 7071091 (2006-07-01), Clarke et al.
patent: 2001/0019903 (2001-09-01), Shufflebotham et al.
patent: 2003/0176055 (2003-09-01), Wu
patent: 2003/0183940 (2003-10-01), Noguchi et al.
patent: 2004/0084749 (2004-05-01), Pamler et al.
patent: 2004/0124446 (2004-07-01), Borger et al.
patent: 2005/0012219 (2005-01-01), Liou
patent: 2005/0067673 (2005-03-01), Geffken et al.
patent: 2005/0074961 (2005-04-01), Beyer et al.
patent: 2005/0079700 (2005-04-01), Schindler et al.
patent: 2006/0057835 (2006-03-01), Anderson et al.
patent: 2006/0084236 (2006-04-01), Vogt
patent: 2006/0105581 (2006-05-01), Bielefeld et al.
patent: 4118165 (1991-12-01), None
patent: 199 57 302 (2001-05-01), None
patent: 10109778 (2002-09-01), None
patent: 101 25 019 (2002-12-01), None
patent: 101 40 754 (2003-03-01), None
patent: 102 46 830 (2004-02-01), None
patent: 103 41 544 (2005-04-01), None
patent: 10 2004 003 337 (2005-08-01), None
patent: 06-216122 (1994-08-01), None
patent: WO 02/095820 (2002-11-01), None
patent: WO 03/019649 (2003-03-01), None
patent: WO 03/102264 (2003-12-01), None
patent: WO 2005/071739 (2005-08-01), None
Arnal, V., et al., “Integration of a 3 Level Cu-SiO2 Air Gap Interconnect for Sub 0.1 micron CMOS Technologies,” IEEE, 2001, 3 pages.
Gabric Zvonimir
Pamler Werner
Schindler Guenther
Steinlesberger Gernot
Stich Andreas
Infineon - Technologies AG
Loke Steven
Slater & Matsil L.L.P.
Thomas Kimberly M
LandOfFree
Method for manufacturing a layer arrangement and layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a layer arrangement and layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a layer arrangement and layer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4156619