Method for manufacturing a highly integrated semiconductor devic

Details Method for manufacturing a highly integrated semiconductor devic Method for manufacturing a highly integrated semiconductor devic

1992-04-14

1993-07-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 60, 437228, 437919, H01L 21265, H01L 2170

Patent

active

052273229

ABSTRACT:
Disclosed is a method comprising forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an etching mask on the conductive layer, etching the conductive layer and defining the conductive layer into cell units; and forming a dielectric film and a second electrode or the first electrode. Also disclosed is a method comprising forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an etching mask on the conductive structure and etching the conductive structure; and forming a dielectric film and a second electrode on the first electrode. An insulating layer including pin holes such as a silicon nitride layer is formed on the conductive structure or the conductive layer; which is exposed under an oxidative atmosphere. The surface portion of the conductive structure or conductive layer is oxidized to form silicon oxide islands to be used as an etching mask. Since the method requires no specific process conditions, it is simple and extends the effective area of the cell capacitor, and is also applicable to various capacitor types.

REFERENCES:
patent: 5068199 (1991-11-01), Sandhu
Mine et al., "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 137-140.

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