Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-03-02
2002-01-01
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S700000, C438S724000, C438S740000, C438S749000
Reexamination Certificate
active
06335285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device providing global planarization between a cell region and a periphery region using a chemical mechanical polishing (CMP) process.
2. Description of the Related Art
The semiconductor device has entered an era of ultra-large-scale integration (ULSI) represented by 256 megabit DRAMs or 1 gigabit DRAMs toward high function, high performance and high integration. Since finer pattern formation technology is necessary for high integration of devices and three-dimensional multiple layered structures are required in various fields, introduction of new processes are being examined.
When ultra-fine interconnection lines are multilayered by a pattern formation technology, it is necessary to planarize an interlevel dielectric layer being under the interconnection lines. To this end, partial planarization has been employed. However, to enhance wafer fabrication performance or manufacture of high quality products, a chemical mechanical polishing (CMP) process for planarization throughout the entire surface of a wafer, i.e., global planarization, needs to be introduced.
In manufacturing a semiconductor device, the cases of forming fine patterns on a complete planar silicon substrate, and forming fine patterns on an uneven substrate formed by already existing patterns, are quite different. The presence of unevenness causes inhomogeneity in an interface between the substrate and a mask, and makes it impossible to attain a desirable pattern preciseness. Thus, various measures for partially alleviating unevenness have been taken.
FIGS. 1 through 3
are cross-sectional views for illustrating a conventional method for planarizing a cell array region and a periphery region using a chemical mechanical polishing process.
First, referring to
FIG. 1
, an isolation layer
4
for defining an active region and a field region is formed on a semiconductor substrate
2
containing a cell array region and a periphery region using a conventional isolation technology. Next, a transistor comprised of a gate insulation layer (not shown), gate electrodes
6
and
8
, and source/drain (not shown) is formed in the active region of the semiconductor substrate
2
.
Subsequently, an insulation material, e.g., silicon nitride, is deposited on the semiconductor substrate where the transistor is formed, and then an insulation layer
10
having a space is formed. The insulation layer
10
is for forming a contact hole in a self-aligning manner during a subsequent step.
Next, an insulation material providing easy planarization, e.g., boron phosphorus silicate glass (BPSG), is deposited over the entire surface of the semiconductor substrate having the insulation layer
10
, and then thermally treated at a predetermined temperature to form an interlevel dielectric layer
12
. Next, a CMP process is performed on the interlevel dielectric layer
12
to planarize the same. The part indicated by the dotted line represents an interlevel dielectric layer before being planarized.
Referring to
FIG. 2
, a photoresist pattern (not shown) is formed on the planarized interlevel dielectric layer
12
and then the interlevel dielectric layer
12
is patterned using the photoresist pattern as a mask, thereby forming a contact hole
14
exposing a source or drain region (not shown) of the semiconductor substrate
2
.
Referring to
FIG. 3
, a conductive material, e.g., an impurity-doped polysilicon layer, is deposited on the resultant structure having the contact hole, and then the polysilicon of the periphery region is removed. Next, a CMP process is performed on the polysilicon layer deposited on the cell array region, thereby forming a conductive pad
16
whose surface is planarized. The CMP process performed on the polysilicon layer employs the interlevel dielectric layer
12
as a stopper. The part indicated by the dotted line represents a polysilicon layer before being planarized.
According to the conventional method, a step difference between the cell array region and the periphery region is removed by performing the CMP process twice, thereby providing global planarization. However, the conventional method for manufacturing a semiconductor device consists of deposition and flow of an interlevel dielectric layer, a first CMP process for the interlevel dielectric layer, contact formation, deposition of a polysilicon layer, and a second CMP process for a pad polysilicon layer, that is, two CMP processes are necessary. Thus, the manufacturing process is complicated, and several defects, i.e., micro scratches on a substrate due to repeated CMP processes, or bridges due to the micro scratch, may be generated.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method for manufacturing a semiconductor device which can provide global planarization between a cell array region and a periphery region by a single CMP process.
Accordingly, to achieve the above objective, first, an interlevel dielectric layer is formed over the entire surface of a semiconductor substrate where a global step difference exists between a cell array region and a periphery region. A first material layer serving as a stopper is formed on the interlevel dielectric layer. A contact hole partially exposing the semiconductor substrate of the cell array region is formed by patterning the first material layer and the interlevel dielectric layer. A conductive layer is formed over the entire surface of the semiconductor substrate where the contact hole is formed. Global planarization is provided between the cell array region and the periphery region by performing a chemical mechanical polishing (CMP) process on the semiconductor substrate where the conductive layer is formed.
When forming the interlevel dielectric layer, a flowable insulation layer, e.g., boron phosphorus silicate glass (BPSG), is deposited over the entire surface of the semiconductor substrate where the global step difference exists between the cell array region and the periphery region, and the insulation layer is flowed by thermally treating the same at a predetermined temperature.
The first material layer is preferably formed of a silicon nitride layer or a silicon oxynitride layer, and is preferably formed to a thickness of 50~2,000Å. Also, the conductive layer is preferably formed of a polysilicon layer. Preferably, the step of etching back the conductive layer is followed by the step of forming the conductive layer. Here, the step of etching back the conductive layer is preferably performed until the conductive layer formed in the periphery region is removed.
The CMP process is performed under the condition that an etching selectivity of the interlevel dielectric layer to the conductive layer to the first material layer is 100-200:100-200:5-50. Here, the CMP process is preferably performed using the first material layer of the periphery region as a stopper. Otherwise, the CMP process is preferably performed until the first material layer of the periphery region is removed.
Also, before forming the interlevel dielectric layer, the method according to the present invention further comprises the steps of sequentially forming a gate insulation layer and gate electrodes on the semiconductor substrate, //forming a source/drain on the semiconductor substrate using the gate electrodes as a mask, and //forming a spacer at side walls of the gate electrodes. The gate electrodes are formed by depositing polysilicon and silicide, and the spacer is preferably formed of a silicon nitride layer.
According to the present invention, a stopper layer is formed using a material which can suppress a CMP process on the interlevel dielectric layer, thereby achieving global planarization between the cell array region and the periphery region by a single CMP process.
REFERENCES:
patent: 5874756 (1999-02-01), Ema et al.
patent: 5943581 (1999-08-01), Lu et
Chun Kwang-youl
Lee Yoon-jae
Noh Jun-yong
Kunemund Robert
Perez-Ramos Vanessa
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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