Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-11-28
2002-03-12
Christian, Keith (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S261000, C438S287000, C438S299000
Reexamination Certificate
active
06355548
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
Priority is claimed from Republic of Korean Patent Application No. 99-60547 filed Dec. 22, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a gate structure incorporated therein a high K dielectric.
2. Description of the Prior Art
As is well known, a semiconductor device has been down-sized by a scale down of a design rule. Therefore, a gate oxide tends to rapidly approach 30 Å in thickness and below to increase the capacitance between a gate electrode and a channel region. However, the use of silicon dioxide as a gate dielectric is limited at this thickness and below. Once silicon dioxide is formed to a thickness of less than 40 angstroms, direct tunneling may occur through the gate dielectric to the channel region, thereby increasing a leakage current associated with the gate electrode and the channel region, causing an increase in power consumption.
Since reducing the thickness of the gate dielectric inherently increases the gate-to-channel leakage current, alternative methods have been developed to reduce this leakage current while maintaining thin SiO
2
equivalent thickness. One of these methods is to use a high K dielectric material such as Ta
2
O
5
as the gate dielectric materials to increase the capacitance between the gate and the channel.
However, if a poly-silicon is utilized as a gate electrode, the use of Ta
2
O
5
for gate dielectric materials has a disadvantage in integrating the semiconductor device. That is, an undesired SiO
2
is formed at an interface between Ta
2
O
5
and the poly-silicon, which, in turn, increases an equivalent oxide thickness. In order to overcome this problem, a barrier metal such as TiN is employed. However, the TiN makes a threshold voltage shift changed.
Therefore, there is still a demand for developing a high K dielectric as a gate oxide with excellent leakage current as well as a low interface state with both a gate electrode and a silicon substrate.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a gate structure incorporated therein a high K dielectric for use in a semiconductor device.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a gate structure for use in a semiconductor device, the method comprising the steps of: a) preparing a semiconductor substrate provided with an isolation region formed therein; b) forming an aluminum nitride (AlN) layer on top of the semiconductor substrate; c) annealing the AlN layer to convert into an Al
2
O
3
layer; d) forming a conductive layer on top of the Al
2
O
3
layer; and e) patterning the conductive layer and the Al
2
O
3
layer into the gate structure.
REFERENCES:
patent: 5707901 (1998-01-01), Cho et al.
patent: 6200866 (2001-03-01), Ma et al.
patent: 6208000 (2001-03-01), Tanamoto et al.
Chen Jack
Christian Keith
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
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