Method for manufacturing a field effect transistor using an auxi

Details Method for manufacturing a field effect transistor using an auxi Method for manufacturing a field effect transistor using an auxi

1997-08-06

1999-09-28

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

438167, 257194, H01L 21302

Patent

active

059602694

ABSTRACT:
In a method for manufacturing a field effect transistor, a semiconductor layer sequence is grown that has a channel layer (2), a barrier layer (3) and a highly doped InGaAs layer (6) suitable for low-impedance contacting to a metal contact. A passivation layer (8) of dielectric is applied and is structured for the region lying between source, gate and drain. An auxiliary layer (10) is applied by vapor-deposition in a very flat incident angle such that the gate region remains free. The semiconductor layers are etched out in the region of the gate down onto the barrier in a plurality of RIE etching processes. The auxiliary layer is removed, spacers are produced at the sidewalls of the passivation layer, a refractory metallization is deposited surface-wide and etched back in planarizing fashion, so that separate contacts for source, gate and drain derive. Finally, the terminal metallization is applied. An alternative embodiment provides that a layer sequence composed of a thin dielectric layer and of at least polyimide or metal layer be provided for the passivation layer (8). After the application of the terminal metallization, the polyimide or metal parts of the passivation layer are removed, so that only a thin passivation layer remains between the terminal contacts for minimizing parasitic capacitances.

REFERENCES:
patent: 4377899 (1983-03-01), Otani et al.
patent: 5539222 (1996-07-01), Le et al.
patent: 5869364 (1999-02-01), Nakano et al.

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