Method for manufacturing a CMOS semiconductor device

Details Method for manufacturing a CMOS semiconductor device Method for manufacturing a CMOS semiconductor device

1994-12-08

1996-01-16

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 46, 437 48, 437 51, 437 56, 148DIG82, H01L 218238, H01L 218244

Patent

active

054847397

ABSTRACT:
A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.

REFERENCES:
patent: 4375999 (1983-03-01), Nawata et al.
patent: 4497106 (1985-02-01), Momma et al.
patent: 4988633 (1991-01-01), Josquin
patent: 5128272 (1992-07-01), Ramde

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