Method for manufacturing a capacitor structure of a semiconducto

Details Method for manufacturing a capacitor structure of a semiconducto Method for manufacturing a capacitor structure of a semiconducto

1994-04-08

1996-02-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054911036

ABSTRACT:
A method for manufacturing a capacitor structure of a highly integrated semiconductor memory device. A first conductive layer is formed on a semiconductor substrate, and a first pattern is formed on the first conductive layer. A first material layer is formed on the resultant structure whereon the first pattern is formed, and the first material layer is etched anisotropically, to thereby form a spacer on the side of the first pattern. After etching the first conductive layer using the spacer as an etch-mask, the first pattern is removed. A second conductive layer is formed on the resultant structure and etched anisotropically. The spacer is removed, to thereby form a storage electrode of a capacitor. The distance between neighboring capacitors can be minimized to a value smaller than the limitation imposed by the lithographic technique, to thereby maximize the area of the capacitor.

REFERENCES:
patent: 5084405 (1992-01-01), Fazan et al.
patent: 5266512 (1993-11-01), Kirsch
patent: 5346844 (1994-09-01), Cho et al.

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