Method for manufacturing a capacitor of an integrated semiconduc

Details Method for manufacturing a capacitor of an integrated semiconduc Method for manufacturing a capacitor of an integrated semiconduc

1992-12-18

1994-10-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053588886

ABSTRACT:
A method for manufacturing a capacitor of a highly integrated semiconductor memory device includes the steps of forming a conductive layer on the whole surface of a semiconductor substrate, forming a first material layer on the whole surface of the conductive layer, forming a polysilicon layer having hemispherical grains on the whole surface of the first material layer, forming a first material layer pattern by performing an etching on the first material layer, using the polysilicon layer as an etch-mask, partially removing the conductive layer by anisotropically etching the conductive layer, using the first material layer pattern as an etch-mask, defining the conductive layer into an individual unit cell, and removing the first material layer pattern. Since greater cell capacitance can be secured by a simple process, this method can be adopted to manufacturing semiconductor memory devices having packing densities up to 64 Mb and 256 Mb.

REFERENCES:
patent: 5134086 (1992-07-01), Ahn
patent: 5204280 (1993-04-01), Dhong et al.
A Capacitor-Over-Bit-line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs, by M. Sakao et al., IGDM 1990, pp. 655-658.
A New Stacked Capacitor DRAM Cell Characterized By A Storage Capacitor On A Bit-Line Structure S. Kimura, Y. Kawamoto, T. Kure, N. Hasegawa, J. Etoh, M. Aoki, E. Takeda, Hl. Sunami & K. Itoh; 1988 Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185 Japan.

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