Method for manufacturing a capacitor for a semiconductor arrange

Details Method for manufacturing a capacitor for a semiconductor arrange Method for manufacturing a capacitor for a semiconductor arrange

1998-02-27

2000-02-08

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438397, 361313, H01L 2120

Patent

active

060227869

ABSTRACT:
For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

REFERENCES:
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5168073 (1992-12-01), Gonzalez et al.
Patent Abstracts of Japan Publication No. 042 085 28--Publication date Jul. 30, 1992--Okamoto Tetsumasa.

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