Method for manufacture semiconductor devices

Details Method for manufacture semiconductor devices Method for manufacture semiconductor devices

1999-04-14

2002-07-30

Chaudhuri, Olik (Department: 2813)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C314S025000

Reexamination Certificate

active

06426174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices in which a semiconductor substrate is exposed so as to form an interconnection pattern for forming a desired circuit.
2. Description of Related Art
Nowadays, IC's (Integrated Circuit) having electronic circuits, which are incorporated in every electronic apparatus, are essential for minimization and upgrading of electronic apparatus. A semiconductor substrate consisting of a material such as silicon is exposed to a light with interposition of an exposure pattern for forming a predetermined circuit to form interconnection patterns, and is processed through development and other prescribed processes to manufacture an IC. In manufacturing an interconnection pattern, it is required that the correction magnitude of the variation of the focus position (referred to as focus hereinafter) that is the distance to a semiconductor substrate and the sensitivity variation (the sensitivity is corrected by correcting, for example, exposure), which vary during manufacturing, are fed back to an exposure apparatus in order to adjust the interconnection width of interconnection patterns to the target interconnection width, and thus the exposure condition is optimized.
A conventional method in which test samples are subjected to exposure before manufacturing of the IC as the product to determine the exposure condition for exposure of the interconnection pattern for forming a circuit has been used. In this method, it is needed that the focus and sensitivity variation with step-wise variation of the focus and exposure energy (referred to as exposure quantity) of an exposure apparatus is calculated previously to calculate the optimal correction magnitude as the preparative work (referred to as condition prediction). The condition prediction leads to increased work and causes poor TAT (Turn Around Time).
Another exposure method in which the above-mentioned condition prediction is not required to avoid poor TAT has been known. In this method, the exposure quantity and the interconnection width after exposure of the interconnection pattern (finished) are monitored on every lot manufactured in the past in order to predict the exposure condition of semiconductor devices manufactured under control of sensitivity variation trend, and the exposure condition is thereby determined.
FIG. 12
is a flow chart for describing yet another conventional exposure method.
In the conventional exposure method, first a predetermined exposure pattern having a prescribed interconnection pattern is exposed on a semiconductor substrate (step ST
21
). The interconnection width of the exposed interconnection pattern is measured (step ST
22
). The difference between the target interconnection width and the actual resultant interconnection width is detected to determine the sensitivity deviation (step ST
23
). If no sensitivity deviation is detected (OK), then the execution is brought to an end (step ST
26
), and otherwise if sensitivity deviation is detected, then the exposure correction magnitude &Dgr;E is calculated from the difference detected (step ST
24
). The exposure quantity is corrected based on the exposure correction magnitude &Dgr;E (step ST
25
).
In the trend control according to the above-mentioned exposure method, when a variation of the interconnection width off the specification is detected in the trend control of the sensitivity variation (for example, lots
6
and
10
in FIGS.
11
A and
11
B), to fit it to the target interconnection width (target interconnection width shown in
FIG. 14
) that is the target of the interconnection pattern after exposure, the exposure quantity is calculated from the exposure quantity versus interconnection width characteristic curve which has been obtained previously. This correction value is fed back to the exposure apparatus to vary the exposure condition. Also in the case in which the wring width of manufactured semiconductor devices is measured to perform trend control for fine correction even if variation of the interconnection width of interconnection pattern after exposure off the specification is detected, correction is performed based on the exposure quantity.
However, because the deviation in interconnection width is corrected only by varying the exposure quantity in this exposure method, the deviation in focus is not corrected, and it causes the following problem.
FIG. 13A
is a finished interconnection width characteristics of an interconnection pattern for simultaneous variation of the sensitivity and focus.
FIG. 13B
is a finished interconnection width characteristics after correction of an interconnection pattern obtained when the deviation is corrected only by varying exposure quantity for simultaneous variation of the sensitivity and focus.
In FIG.
13
A and
FIG. 13B
, the axis of abscissa represents the focus and the axis of ordinate represents the interconnection width (line width).
Correction according to the conventional exposure method shown in
FIG. 12
shows the result that the actual line width is within the allowance of the target line width for sparse pattern, but the actual line width exceeds the allowable upper limit of the line width specification for uncontrolled dense pattern because the correction depends on only exposure quantity &Dgr;E. Though the actual line width is within the allowance for the sparse pattern, the focus versus interconnection width characteristics fluctuates and the variation of focus affects the stability of the exposed interconnection width significantly because the focus deviation remains as it was.
The interconnection width characteristics j and k represents the interconnection width characteristics of two interconnection patterns which are different in the density of finished interconnection width. The interconnection width characteristics j represents the interconnection width characteristics of the sparse interconnection pattern, on the other hand, the interconnection width characteristics k represents the interconnection width characteristics of the dense interconnection pattern.
On a semiconductor substrate which is a component of a semiconductor device, various interconnection patterns different in the line density are formed actually. Therefore, the interconnection width characteristics versus focus depends on the line density of the interconnection pattern.
When a exposure pattern served as a transfer pattern for forming a circuit on a semiconductor substrate by exposure is copied on a semiconductor substrate by exposure, the focus versus interconnection width characteristics changes gradually from the mountain-shape to the valley-shape as shown in the order from
FIG. 5B
, to
FIG. 6B
, and
FIG. 7B
as the interconnection pattern becomes denser as shown in the order from
FIG. 5A
, to
FIG. 6A
, and FIG.
7
A.
In the case that the focus F deviates from the ideal focus F
1
as shown in
FIG. 13A
, though the position on X-axis at the inflection point of the interconnection width characteristics corresponds to the ideal focus F
1
, the focus which is actually exposed to a light in manufacturing process corresponds to the vertical dotted line F (the difference &Dgr;F between the focus F shown with the dotted line and the above-mentioned ideal focus F
1
is referred to as focus deviation hereinafter).
The above-mentioned situation causes the difference in finished interconnection width after exposure between the sparse interconnection width characteristics and the dense interconnection width characteristics. Correction of the exposure quantity by exposure correction magnitude &Dgr;E only moves the interconnection width characteristics k and the interconnection width characteristics j vertically (in the direction of interconnection width) along the axis of ordinate in the graph shown in
FIG. 13A
, and it is impossible to solve the finished interconnection width difference due to the above-mentioned focus deviation &Dgr;F.
In this exposure method, only the interconnection width char

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