Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1993-01-15
1998-10-20
Teska, Kevin J.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711220, 711203, G06F 1208
Patent
active
058260579
ABSTRACT:
A method for managing virtual address space in which programs designed for smaller virtual address spaces in the multiple virtual memory scheme can be collectively allocated to a single enlarged virtual address space in the single virtual memory scheme efficiently, without requiring any change in the programs themselves, such that the entire virtual address space becomes available in the compatible mode. In the method, the effective addresses to be used during an execution of a program designed for a smaller address space are calculated by combining an appropriate address base for this program specifying upper bits of the effective address and lower bits of the virtual addresses for a region of the enlarged address space to which this program is allocated. The address base may be replaced by the upper bits of the starting address of the program in the enlarged address space which are retained throughout the effective address calculation. The method may use a compatible mode address region to be used in executing a program designed for a smaller address space which has virtual addresses identical to those to which this program is designed to be allocated in the smaller address space.
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Okamoto Toshio
Saito Mitsuo
Segawa Hideo
Wakamori Osamu
Kabushiki Kaisha Toshiba
Loppnow Matthew
Teska Kevin J.
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