Method for managing multiple DMA queues by a single controller

Details Method for managing multiple DMA queues by a single controller Method for managing multiple DMA queues by a single controller

1997-11-04

1999-08-17

Shin, Christopher B.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710129, G06F 1300

Patent

active

059387440

ABSTRACT:
The present invention provides a method and apparatus whereby a single engine can manage multiple DMA queues and related functions for a mass storage subsystem such as a RAID array. By operating the engine at a suitably high clock rate, the key buses may be time multiplexed such that each bus operates at substantially its optimum frequency to maintain high efficiency of data throughput. To improve performance further, the DMA addressing function is allocated additional phases whenever the remaining buses have not requested access to the RAID engine.

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