Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-18
2002-05-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C326S101000
Reexamination Certificate
active
06397375
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to interconnect routing in integrated circuit design, and more particularly to a method for managing the metal resources used in over-the-block routing in integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits comprise a plurality of electronic components that function together to implement a higher-level function. ICs are formed by implanting a pattern of transistors into a silicon wafer which are then connected to each other by layering multiple layers of metal materials, interleaved between dielectric material, over the transistors. The fabrication process entails the development of a schematic diagram that defines the circuits to be implemented. A chip layout is generated from the schematic. The chip layout, also referred to as the artwork, comprises a set of planar geometric shapes over several layers that implement the circuitry defined by the schematic. A mask is then generated for each layer based on the chip layout. Each metal is then successively manufactured over the silicon wafer according to the layer's associated mask using a photolithographical technique.
The process of converting the specifications of an electrical circuit schematic into the layout is called the physical design process. CAD tools are extensively used during all stages of the physical design process. The physical design process is accomplished in several stages including partitioning, floorplanning, and routing.
During the partitioning stage, the overall integrated circuit is partitioned into a set of functional subcircuits called blocks. The block partitioning process considers many factors including the number and size of the blocks, and number of interconnections between the blocks. The output of partitioning is a set of blocks along with a set of interconnections required between blocks, referred to herein as a netlist.
During the floorplanning stage, a floorplan is developed defining the placement and rectangular shape of each block. The goal of the floorplanning stage is to select the optimal layout for each block, as well as for the entire chip.
Once an acceptable floorplan is developed, the interconnections between the blocks (as defined by the netlist) are routed. The space not occupied by the blocks is partitioned into rectangular regions referred to as channels. Interconnects are preferably routed within the designated channels, but may also be routed through defined feedthroughs through the blocks, or in defined over-the-block routing space.
The goal of a router is to complete all circuit connections resulting in minimal interconnect signal delay. Where possible, the router will generally attempt to route individual interconnects on a single layer; however, if this is not achievable given the topology of the netlist, an interconnect may be routed over two or even more layers. Often, interconnect routes resulting from the autorouting will be too long to meet signal delay specifications. The delay results from the inherent RC characteristics of the interconnect line.
Over the past decades, integrated circuits (ICs) of increasingly higher density have been developed to meet industry demands of higher performance and smaller packaging. The very high densities of today's integrated circuits means that more metal layers and interconnects per layer are required than ever before. The result is that the routing task has become even more complex.
Generally, the lowest level metal layers are used by local block interconnects, i.e., intra-block signals, and higher-level metal layers are used by inter-block interconnects. Each layer includes a power grid and clock distribution signals. In high density integrated circuits, all of the intra-block routing often cannot be achieved within the lowest level metal layers. Accordingly, metal in the higher layers must often be reserved for intra-block routing.
It is clear from this description that several distinct route types compete for the available metal resources in the different metal layers. In this respect, the power grid, the clock distribution system, the intra-block routing, and the global inter-block routing all compete for metal on some, if not all, of the metal layers. Therefore, unless metal tracks in each of the higher-level metal layers are specifically set aside on each of those layers for each of the respective routing types, the auto-router may not be able to find a complete or satisfactory routing solution.
In the prior art, a number of metal tracks in each layer are pre-allocated for use by each of the different route types. Once a track is pre-allocated for use by a particular route type, its use must remain for that purpose. Block designers must design the blocks to interface with the pre-assigned track assignment, which therefore often limits the different combinations of placement of signal ports and sub-blocks within the block. Accordingly, optimal placement of sub-blocks often cannot be achieved. In addition, since the track assignments are immutable, blocks that require more upper-layer intra-block interconnects often must occupy more chip space just to be able to connect to pre-allocated intra-block tracks on those layers. Similarly, blocks that require less upper-layer intra-block interconnects often do not fully utilized pre-allocated intra-block tracks that pass over them. Accordingly, it is clear that the density of the chip is directly affected by the efficiency of use of the upper-level metal layers.
It is therefore an object of the invention to provide a metal management methodology that makes more efficient use of the available metal in each layer.
SUMMARY OF THE INVENTION
The present invention is a novel method and system for managing metal resources during over-the-block routing of an integrated circuit.
The metal management methodology enables advantages in efficiency over the prior art. The communication between block designers as to the block routing requirements facilitates better placement of sub-blocks and signal ports. This results in more efficient use of over-the-block routing metal, as well as facilitates the ability to create higher density blocks. In addition, the allowance of multi-use tracks in over-the-block routing results in less unused metal and therefore also allows higher density blocks.
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Block Adam Stuart
Josephson Don D
Witte Jeffrey P
Hewlett--Packard Company
Kik Phallaka
Smith Matthew
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