Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-02-15
2005-02-15
Vital, Pierre M. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S142000, C711S143000
Reexamination Certificate
active
06857049
ABSTRACT:
A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache memory is a store-in memory. Therefore, when data is to be deleted from the second level cache memory, a determination is made whether the data has been modified by the processor. If the data has been modified, the data must be rewritten to lower level memory. To free the second level cache memory for storage of the newly requested data, the data to be flush is loaded into a flush buffer for storage during the rewriting process.
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Englin Donald C.
Federici James L.
Vartti Kelvin S.
Johnson Charles A.
Nawrocki, Rooney & Sivertson P.A.
Starr Mark T.
Unisys Corporation
Vital Pierre M.
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