Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-11-12
1999-12-07
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438652, 438642, 438666, H01L 214763
Patent
active
059982926
ABSTRACT:
The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.
REFERENCES:
J. Carson, "The Emergence of Stacked 3D Silicon and Its Impact on Microelectronics Systsms Integration," Proceedings of Eighth Annual IEEE International Conference on Innovative Systems in Silicon, p. 1 (1996).
K. Yamazaki, et al., "4-Layer 3-D IC Technologies For Parallel Signal Processing," Tech. Dig. of IEDM, p. 599 (1990).
K. Kioi, et al., "Design and Implementation of a 3D-LSI Character Recognition Image Sensor," Tech. Dig. of IEDM, p. 279 (1990).
T. Kunio, et al., "Three Dimensional ICs, Having Four Stacked Active Device Layers," Tech. Dig. of IEDM, p. 837 (1989).
Black Charles Thomas
Burghartz Joachim Norbert
Tiwari Sandip
Welser Jeffrey John
International Business Machines - Corporation
Nguyen Tuan H.
Schecter Manny W.
Thompson Craig
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