Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-03-24
2001-11-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S762000, C438S763000, C438S253000, C438S296000, C438S238000, C257S133000, C257S411000
Reexamination Certificate
active
06323143
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors with deep submicrometer channel lengths.
(2) Description of the Prior Art
Advances in the semiconductor process technologies in the past few years have dramatically decreased the device feature sizes and increased circuit density on integrated circuit chips. The device used the most for these Ultra Large Scale Integration (ULSI) applications is the Field Effect Transistor (FET) which consists of a polysilicon or polycide gate electrode formed over a thin gate oxide with self-aligned source/drain contact areas. The popular choice of FETs is because of their very small size, high packing density, low power consumption, high yields, and low cost of manufacturing.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single-crystal semiconductor substrate. As the size of the polysilicon gate electrode structure is scaled down in the horizontal direction to provide submicrometer FET channel lengths to increase circuit density and speed, it is also necessary to scale back in the vertical dimensions. Therefore it is necessary to form more shallow source/drain junctions and it is also necessary to reduce the gate oxide thickness (T
ox
) for reduced gate voltage (V
g
).
However, as the FETs are down scaled to submicrometer channel length, the FET device experiences a number of undesirable electrical characteristics results. Besides the need to minimize the various short channel effects, it is also necessary to minimize the oxide leakage current through the FET ultra-thin gate oxide. As the gate oxide thickness is scaled down approaching thicknesses less than 16 Angstroms, direct electron tunneling through the gate oxide occurs. When this oxide leakage current becomes comparable to the FET off-current (I
off
), the standby power for the FET becomes unacceptably high.
Numerous methods for making improved ultra-thin gate oxides have been reported in the literature. For example, in U.S. Pat. No. 5,324,675 to Hayabuchi, a method is described for making a MONOS (metal-oxide
itride/oxide-silicon) gate insulating layer for non-volatile memory. The method grows a thin oxide and deposits a silicon nitride. The silicon nitride is then partially oxidized to form an oxide
itride/oxide gate oxide for non-volatile memory. A polysilicon gate electrode and the thin silicon nitride layer adjacent to the gate electrode are oxidized to from a silicon oxide which can be removed without damaging the source/drain areas. The oxide
itride/oxide gate insulating layer remains under the gate electrode to form a non-volatile memory cell. Another method of making thin gate oxides is described in U.S. Pat. No. 5,650,344 to Ito et al. and in U.S. Pat. No. 5,808,348 to Ito et al. Ito teaches a method for a non-uniform nitrided gate oxide structure in which the gate insulating layer remains essentially pure silicon oxide under the center of the gate electrode while the gate insulator is nitrogen-rich at the edge of the gate electrodes.
In recent years there has been an increasing interest in making ultra-thin gate oxides using a new low-pressure (reduced pressure) rapid thermal process (LP-RTP) technique, commonly referred to as in-situ steam generation (ISSG). In this method an in-situ steam is generated from ultra-pure hydrogen (H
2
) and oxygen (O
2
) at low pressures to controlably grow gate oxides that are less than 25 Angstroms thick.
However, there is still a strong need in the semiconductor industry to form ultra-thin gate oxides for FETs with improved low leakage currents and with increased processing latitude (windows) using LP-RTP while maintaining a cost-effective manufacturing process.
SUMMARY OF THE INVENTION
It is a principal object of this invention to provide a novel nitride-oxide ultra-thin gate insulating layer for field effect transistors with reduced leakage currents and is compatible with current dual-gate oxide processes.
It is another object of this invention to form this ultra-thin nitride-oxide gate insulating layer using a novel low-pressure rapid thermal process and an ultra-thin silicon nitride layer that also reduces or prevents boron penetration.
It is still another object to provide a process with an increased process window by using this ultra-thin silicon nitride (Si
3
N
4
) layer followed by a low-pressure re-oxidation rapid thermal process (RTP) in a nitrogen-rich oxidation ambient (dinitrogen oxide N
2
O) as the oxidation gas. The non-self-limiting characteristic of the ultra-thin silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a silicon oxide layer on and in the substrate surface.
In accordance with the above objects, a method for fabricating improved ultra-thin gate oxides for deep sub-micrometer FETs having channel lengths of less than 0.18 micrometers (&mgr;m) is provided. The method results in a very controllable ultra-thin silicon nitride-oxide gate insulating layer (about 18 to 30 Angstroms thick) that also reduces the gate oxide leakage currents and boron penetration. The method also provides a means of forming a very controllable interface silicon oxide layer at the substrate surface while providing a nitrogen-rich oxidized silicon nitride layer. The method for forming this improved FET nitride-oxide gate insulating layer begins by providing a semiconductor substrate consisting of single-crystal silicon and having device areas that are typically surrounded and electrically isolated by field oxide areas. A thin silicon nitride layer is grown on the substrate surface in the device areas. The silicon nitride layer is formed in a low-pressure rapid thermal process (RTP) by applying a first heating step while subjecting the substrate to a first gas ambient containing nitrogen, such as ammonia (NH
3
), while insuring that the RTP chamber is free of oxygen. The silicon nitride layer is then subjected to a oxidation second heating step and a second gas ambient containing nitrogen and oxygen. The second gas ambient is preferably dinitrogen oxide (N
2
O), and the second heating step is at a sufficiently high temperature to form a silicon oxide (SiO
2
) layer at the interface between the silicon nitride layer and the substrate an the device areas. Concurrently the oxidation is carried out in the nitrogen-rich gas (N
2
O) to retain a high nitrogen concentration in the oxidized silicon nitride layer This results in an ultra-thin nitrogen-rich silicon nitride-oxide gate insulating layer (about 18 to 30 Angstroms thick) that achieves the above objectives.
REFERENCES:
patent: 4621277 (1986-11-01), Ito et al.
patent: 4623912 (1986-11-01), Chang et al.
patent: 4882649 (1989-11-01), Chen et al.
patent: 5250456 (1993-10-01), Bryant
patent: 5324675 (1994-06-01), Hayabuchi
patent: 5650344 (1997-07-01), Ito et al.
patent: 5663087 (1997-09-01), Yokozawa
patent: 5808348 (1998-09-01), Ito et al.
patent: 6200844 (2001-03-01), Huang et al.
patent: 6207586 (2001-03-01), Ma et al.
patent: 6215163 (2001-04-01), Hori et al.
S. Wolf, Silicon Processing for the VLSI Era 1990, Lattice Press, vol. 1, pp. 57-58.*
S. Wolf, Silicon Processing for the VLSI Era 1990, Lattice Press, vol. 3, pp. 648-660.
Ackerman Stephen B.
Keshavan Belur V
Saile George O.
Smith Matthew
Taiwan Semiconductor Manufacturing Company
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