Method for making semiconductor device having a high-k gate...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S750000

Reexamination Certificate

active

11393151

ABSTRACT:
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

REFERENCES:
patent: 5868330 (1999-02-01), Dodd et al.
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6365450 (2002-04-01), Kim et al.
patent: 6410376 (2002-06-01), Ng et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6620713 (2003-09-01), Arghavani et al.
patent: 6642131 (2003-11-01), Harada
patent: 6667246 (2003-12-01), Mitsuhashi et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 6696327 (2004-02-01), Brask et al.
patent: 6696345 (2004-02-01), Chau et al.
patent: 6727130 (2004-04-01), Kim et al.
patent: 6794234 (2004-09-01), Polishchuk et al.
patent: 6794281 (2004-09-01), Madhukar et al.
patent: 6856288 (2005-02-01), Apostolos et al.
patent: 6858483 (2005-02-01), Doczy et al.
patent: 6893927 (2005-05-01), Shah et al.
patent: 2001/0027005 (2001-10-01), Moriwaki et al.
patent: 2002/0058374 (2002-05-01), Kim et al.
patent: 2002/0197790 (2002-12-01), Kizilyalli et al.
patent: 2003/0032303 (2003-02-01), Yu et al.
patent: 2003/0045080 (2003-03-01), Visokay et al.
patent: 2003/0201121 (2003-10-01), Jeng
patent: 2004/0007723 (2004-01-01), Andoh et al.
patent: 2005/0101113 (2005-05-01), Brask et al.
patent: 2005/0101134 (2005-05-01), Brask et al.
patent: 2005/0136677 (2005-06-01), Brask et al.
patent: 2005/0148130 (2005-07-01), Doczy et al.
patent: 2005/0148136 (2005-07-01), Brask et al.
patent: 2005/0214987 (2005-09-01), Shah et al.
patent: 2005/0221548 (2005-10-01), Doyle et al.
patent: 2005/0250258 (2005-11-01), Metz et al.
patent: 2006/0172497 (2006-08-01), Hareland et al.
patent: 0 899 784 (1999-03-01), None
patent: 1 032 033 (2000-08-01), None
patent: 2 358 737 (2001-04-01), None
patent: 2002-118175 (2002-04-01), None
patent: WO 01/97257 (2001-12-01), None
patent: PCT/US2005/010920 (2005-03-01), None
Chapter I International Preliminary Report on Patentability and Written Opinion from PCT/US2005/010920, mailed Nov. 2, 2006, 8 pgs.
Polishchuk et al., “Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion”, www.eesc.berkeley.edu, 1 page.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
Doczy et al., “Integrating N-type and P-type Metal Gate Transistors,” U.S. Appl. No. 10/327,293, Filed Dec. 20, 2002.
Brask et al., “A Method for Making a Semiconductor Device Having a Metal Gate Electrode,” U.S. Appl. No. 10/704,497, Filed Nov. 6, 2003.
Brask et al., “A Method for Etching a Thin Metal Layer”, U.S. Appl. No. 10/704,498, Filed Nov. 6, 2003.
Brask et al., “A Method for Making a Semiconductor Device with a Metal Gate Electrode that is Formed on an Annealed High-K Gate Dielectric Layer”, U.S. Appl. No. 10/742,678, Filed Dec. 19, 2003.
Brask et al., “A Method for Making a Semiconductor Device that Includes a Metal Gate Electrode”, U.S. Appl. No. 10/739,173, filed Dec. 18, 2003.
Brask et al., “A CMOS Device With Metal and Silicide Gate Electrodes and a Method for Making It”, U.S. Appl. No. 10/748,559, filed Dec. 29, 2003.
Doczy et al., “A Method for Making a Semiconductor Device that Includes a Metal Gate Electrode”, U.S. Appl. No. 10/748,545, filed Dec. 29, 2003.
Shah et al., “A Method for Making a Semiconductor Device with a Metal Gate Electrode,” U.S. Appl. No. 10/805,880, filed Mar. 22, 2004.
Shah et al., “A Replacement Gte Process for Making a Semiconductor Device that Includes a Metal Gate Electrode,” U.S. Appl. No. 10/809,853, filed Mar. 24, 2004.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for making semiconductor device having a high-k gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making semiconductor device having a high-k gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making semiconductor device having a high-k gate... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3955114

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.