Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-08-20
2001-12-25
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C257S758000
Reexamination Certificate
active
06333255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device having a multilevel interconnect structure and a method for fabricating the same, and more particularly relates to techniques for reducing wiring delay.
Currently, the size of a transistor goes on being decreased day by day. It has already been shown that, in transistors for silicon LSI's belonging to the size generation of 0.07 &mgr;m or more, in particular, if 1/k scaling is realized in the lateral direction, the speed thereof can be increased by 1/k.
On the other hand, in multilevel interconnect technology, the contribution of wire-to-wire capacitance is significant if the sizes belong to the generation of about 0.5 &mgr;m or more. Thus, it has already been shown that even if 1/k scaling is realized in the lateral direction, the wiring delay thereof is reduced by no more than 1/k
2−a
, where a is a coefficient having a value from 1 to 2.
In view of the state in the art, a scaling rule for reducing the wiring delay by approximately the same degree as 1/k was suggested. In accordance with the scaling rule, the thickness of a wire is scaled down to 1/k
2/3
, the thickness of an interlayer dielectric film to 1/k
1/2
, the relative dielectric constant of the interlayer dielectric film to 1/k
1/3
and the specific resistance of the wire to 1/k
1/3.
However, if this scaling rule must be obeyed, the relative dielectric constants of materials for an interlayer dielectric film should be decreased to be 3.5, 3.1, 2.8, 2.4 and 1.9 for the 0.35 &mgr;m-generation, 0.25 &mgr;m-generation, 0.18 &mgr;m-generation, 0.13 &mgr;m-generation and 0.10 &mgr;m-generation, respectively.
The relative dielectric constant of a silicon dioxide film, which is widely used as an interlayer dielectric film, is about 4. Thus, so long as this scaling rule must be complied with, a silicon dioxide film can no longer be applied for the generations of 0.35 &mgr;m or less. Among various organic low-dielectric-constant films under development, an HSQ film (2.2), a Teflon-AF film (1.9) and the like have smallest dielectric constants. If the air having a relative dielectric constant of 1 could be used as an alternative to an insulating film, then the speed of a CMOS device with a design rule of 0.35 &mgr;m could be further increased by about 33% as compared with the case of using an HSQ film, for example.
Accordingly, it is considered that the above described various problems might be solved by employing a gas-dielectric interconnect process for disposing wires between the wire-to-wire gaps filled with a gas.
Hereinafter, an exemplary application of a gas-dielectric interconnect process for trench interconnection (suggested by M. B. Anand et al., VLSI Symposium 1996, p. 82) will be described with reference to the drawings.
FIGS.
10
(
a
) and
10
(
b
) are cross-sectional views illustrating a conventional single-damascene gas-dielectric interconnect process, while FIG.
10
(
c
) is a process flow chart thereof. FIGS.
11
(
a
) and
11
(
b
) are cross-sectional views illustrating a conventional dual-damascene gas-dielectric interconnect process, while FIG.
11
(
c
) is a process flow chart thereof. The two types of semiconductor device structures to be formed in accordance with the respective processes will be described below with reference to the process flow charts of FIGS.
10
(
c
) and
11
(
c
).
First, the single-damascene gas-dielectric interconnect process will be described. In the process step shown in FIG.
10
(
a
), a carbon film
102
is formed on a substrate
101
by sputtering, and trenches are formed in the carbon film
102
. Then, a metal film is deposited over the entire surface of the substrate and etched-back, thereby forming a metal interconnect layer
103
so as to fill in the trenches.
Next, in the process step shown in FIG.
10
(
b
), a thin silicon dioxide film
104
is formed over the substrate and then the carbon film
102
is burned to be ashed in a furnace at a temperature from 400° C. to 450° C. while supplying O
2
gas hereto. As a result, the gaps between the wires in the interconnect layer
103
form a gas layer
105
.
Then, a carbon film is deposited over the entire surface of the substrate and a metal film is deposited so as to fill in the via-holes formed in the carbon film, thereby forming plugs to be connected to the respective wires. Thereafter, the process returns to the step shown in FIG.
10
(
a
) and a similar process is repeatedly performed to remove the surrounding carbon film.
In this way, by repeatedly performing the process steps shown in FIGS.
10
(
a
) and
10
(
b
) and the subsequent process step of forming plugs, a gas-dielectric interconnect structure, in which gas layers exist between multilevel interconnects, can be formed.
On the other hand, the dual-damascene gas-dielectric interconnect process is performed in the following manner.
At the outset of the process step shown in FIG.
11
(
a
), the steps shown in FIGS.
10
(
a
) and
10
(
b
) have already been performed to form the (lower) interconnect layer
103
, in which wires are surrounded by the gas layer
105
, and the (lower) silicon dioxide film
104
on the substrate
101
. In such a state, a carbon film
106
is formed by sputtering over the entire surface of the substrate, a thin silicon dioxide film
107
is deposited thereon, and another carbon film
108
is further deposited thereon. Then, trenches are formed through the carbon film
108
and via-holes are formed through the silicon dioxide film
107
and the carbon film
106
. Thereafter, a metal film is deposited over the entire surface of the substrate and etched-back, thereby forming metal plugs
109
and an upper metal interconnect layer
110
so as to fill in the via-holes and the trenches simultaneously.
Next, in the process step shown in FIG.
11
(
b
), a thin silicon dioxide film
111
is formed over the substrate and the two carbon films
106
and
108
are burned to be ashed at a temperature from 400° C. to 450° C. while supplying O
2
gas thereto. As a result, gas layers
113
and
114
are formed to surround the plugs
109
and the wires in the upper interconnect layer
110
.
That is to say, by interposing gas layers as alternatives to low-dielectric-constant films, a multilevel interconnect structure contributing to the reduction of parasitic capacitance is formed.
However, in accordance with the processes shown in FIGS.
10
(
a
) and
10
(
b
) and FIGS.
11
(
a
) and
11
(
b
), the thicknesses of the silicon dioxide films
104
,
107
,
111
should be, sufficiently small such that oxygen can be sequentially permeated downward during ashing and removal of the carbon films
102
,
106
,
108
within an oxygen ambient at about 450° C. in the process steps shown in FIGS.
10
(
b
) and
11
(
b
). Then, the silicon dioxide films cannot show sufficient strength for supporting the respective wires, and therefore the reliability is adversely deteriorated.
In addition, the procedures of repeatedly depositing carbon films, silicon dioxide films and metal films and repeatedly ashing the carbon films to be removed are so complicated that the process efficiency is unsatisfactory.
On the other hand, in order to reduce the specific resistance of a wire and thereby reduce the wiring delay, it is considered that Cu wires should naturally replace Al wires. However, since it is difficult to form Cu wires by dry etching, the steps shown in FIGS.
10
(
a
) and
10
(
b
) and FIGS.
11
(
a
) and
11
(
b
), in which trenches and holes are formed beforehand and then Cu is filled therein, have been taken. As a specific alternative procedure of such a method, a reflow process, in which a Cu film is deposited by sputtering and then made to flow and injected into trenches and holes within a hydrogen ambient at a temperature from 400 to 500° C., is now under development and expected to be used widely. However, since a currently developed a low-dielectric-constant film (e.g., a film having a relative dielectric constant of 2.8 or less) has thermal resistance as low
Chaudhuri Olik
Doan Theresa T.
Matsushita Electronics Corporation
McDermott & Will & Emery
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